Treegion scheduling for highly parallel processors
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Instruction scheduling is a compile-time technique for extracting parallelism from programs for statically scheduled instruction level parallel processors. Typically, an instruction scheduler partitions a program into regions and then schedules each region. One style of region represents a program as a set of decision trees or treegions. The non-linear nature of the treegion allows scheduling across multiple paths. This paper presents such a technique, termed treegion scheduling. The results of experiments comparing treegion scheduling to scheduling for basic blocks and across “simple linear regions” show that treegion scheduling outperforms the other techniques.
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