Treegion scheduling for highly parallel processors

  • Sanjeev Banerjia
  • William A. Havanki
  • Thomas M. Conte
Workshop 17: Instruction-Level Parallelism

DOI: 10.1007/BFb0002855

Part of the Lecture Notes in Computer Science book series (LNCS, volume 1300)
Cite this paper as:
Banerjia S., Havanki W.A., Conte T.M. (1997) Treegion scheduling for highly parallel processors. In: Lengauer C., Griebl M., Gorlatch S. (eds) Euro-Par'97 Parallel Processing. Euro-Par 1997. Lecture Notes in Computer Science, vol 1300. Springer, Berlin, Heidelberg

Abstract

Instruction scheduling is a compile-time technique for extracting parallelism from programs for statically scheduled instruction level parallel processors. Typically, an instruction scheduler partitions a program into regions and then schedules each region. One style of region represents a program as a set of decision trees or treegions. The non-linear nature of the treegion allows scheduling across multiple paths. This paper presents such a technique, termed treegion scheduling. The results of experiments comparing treegion scheduling to scheduling for basic blocks and across “simple linear regions” show that treegion scheduling outperforms the other techniques.

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Copyright information

© Springer-Verlag 1997

Authors and Affiliations

  • Sanjeev Banerjia
    • 1
  • William A. Havanki
    • 1
  • Thomas M. Conte
    • 1
  1. 1.Department of Electrical and Computer EngineeringNorth Carolina State UniversityRaleigh

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