Treegion scheduling for highly parallel processors

  • Sanjeev Banerjia
  • William A. Havanki
  • Thomas M. Conte
Workshop 17: Instruction-Level Parallelism
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1300)

Abstract

Instruction scheduling is a compile-time technique for extracting parallelism from programs for statically scheduled instruction level parallel processors. Typically, an instruction scheduler partitions a program into regions and then schedules each region. One style of region represents a program as a set of decision trees or treegions. The non-linear nature of the treegion allows scheduling across multiple paths. This paper presents such a technique, termed treegion scheduling. The results of experiments comparing treegion scheduling to scheduling for basic blocks and across “simple linear regions” show that treegion scheduling outperforms the other techniques.

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References

  1. 1.
    G. S. Tjaden and M. J. Flynn, “Detection and parallel execution of independent instructions,” IEEE Trans. Comput., vol. C-19, pp. 889–895, Oct. 1970.Google Scholar
  2. 2.
    J. A. Fisher, “Trace scheduling: A technique for global microcode compaction,” IEEE Trans. Comput., vol. C-30, no. 7, pp. 478–490, July 1981.Google Scholar
  3. 3.
    S. A. Mahlke, Exploiting instruction level parallelism in the presence of branches. PhD thesis, Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, Urbana, IL, 1996.Google Scholar
  4. 4.
    B. L. Deitrich and W. W. Hwu, “Speculative hedge: regulating compile-time speculation against profile variations,” in Proc. 29th Ann. Int'l Symp. on Microarchitecture [11].Google Scholar
  5. 5.
    T. M. Conte and S. W. Sathaye, “Dynamic rescheduling: A technique for object code compatibility in VLIW architectures,” in Proc. 28th Ann. Int'l Symp. on Microarchitecture, (Ann Arbor, MI), Nov. 1995.Google Scholar
  6. 6.
    C. Chekuri, R. Johnson, R. Motwani, B. Natarajan, B. Rau, and M. Schlansker, “Profile-driven instruction level parallel scheduling with application to superblocks,” in Proc. 29th Ann. Int'l Symp. on Microarchitecture [11], pp. 58–67.Google Scholar
  7. 7.
    P. Y. T. Hsu and E. S. Davidson, “Highly concurrent scalar processing,” in Proc. 13th Ann. Int'l Symp. Computer Architecture, (Tokyo, Japan), June 1986.Google Scholar
  8. 8.
    A. Nicolau, “Percolation scheduling: a parallel compilation technique,” Technical report TR-678, Department of Computer Science, Cornell University, Ithaca, NY, May 1985.Google Scholar
  9. 9.
    K. Ebcioĝlu, “Some design ideas for a VLIW architecture for sequential-natured software,” in Proceedings of the IFIP Working Group 10.3 Working Conference on Parallel Processing, (Pisa, Italy), pp. 3–21, North Holland, 1988. (published as Parallel Processing, M. Cosuard, et al., (eds).).Google Scholar
  10. 10.
    J. A. Fisher, “Global code generation for instruction-level parallelism: Trace Scheduling-2,” Tech. Rep. HPL-93-43, Hewlett-Packard Laboratories, June 1993.Google Scholar
  11. 11.
    Proc. 29th Ann. Int'l Symp. on Microarchitecture, (Paris, France), Dec. 1996.Google Scholar

Copyright information

© Springer-Verlag 1997

Authors and Affiliations

  • Sanjeev Banerjia
    • 1
  • William A. Havanki
    • 1
  • Thomas M. Conte
    • 1
  1. 1.Department of Electrical and Computer EngineeringNorth Carolina State UniversityRaleigh

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