Euro-Par 1997: Euro-Par'97 Parallel Processing pp 771-778 | Cite as
Scheduling instructions with uncertain latencies in asynchronous architectures
Workshops 10+11+14: Parallel Computer Architecture and Image Processing
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Abstract
This paper addresses the problem of scheduling instructions in micronet-based asynchronous processors (MAP), in which the latencies of the instructions are not precisely known. A PTD scheduler is proposed which minimises true dependencies, and results are compared with two list schedulers — the Gibbons and Muchnick scheduler, and a variation of the Balanced scheduler. The PTD scheduler has a lower time complexity and produces better quality schedules than the other two when applied twenty-three loop- and control-intensive benchmark programs.
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References
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© Springer-Verlag Berlin Heidelberg 1997