Advertisement

IEEE 754-Based Single- and Double-Precision Floating-Point Multiplier Analysis

  • Shoaib Arif ShaikhEmail author
  • B. B. Godbole
  • Ulhas D. Shiurkar
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 1025)

Abstract

In signal processing applications decimal and floating-point arithmetic units are of prominent importance. IEEE has developed the IEEE 754 standard for floating-point calculations. A revised standard IEEE 754r comes in 2008 for floating-point arithmetic units. Different conditions incorporated into the IEEE 754r have originated the novel IEEE 754-2008 standard (Eisen et al. in IBM J Res Dev 51(6):1–21, 2007) [1]. A vital operation in calculations of DFP is the multiplication due to its wide range of uses therefore in current years several decimal multiplication designs in fixed and floating-point have been proposed with different results maintaining a compromise between parameters such as latency and area. Hence studying and proposing innovative multiplication alternatives in DFP format is attractive to find suitable design compromises. This paper presents a general approach to floating-point decimal numbers that are represented in the IEEE 754-2008 standard. For FPGA implementation the Verilog code is developed and synthesized in Xilinx Virtex 4 and 7 series for DFP multiplier.

Keywords

Floating point IEEE 754-2008 DFP FPGA etc. 

References

  1. 1.
    Eisen, L., Ward, J.W., Taste, H.W., Mading, N., Leenstra, J., Mueller, S.M., Jacobi, C., Preiss, J., Schwarz, E.M., Carlough, S.R.: IBM power6 accelerators: Vmx and dfu. IBM J. Res. Dev. 51(6), 1–21 (2007)CrossRefGoogle Scholar
  2. 2.
    Cui, X., Liu, W., Chen, X., Swartzlander, E.E., Lombardi, F.: A modified partial product generator for redundant binary multipliers. IEEE Trans. Comput. 65(4), 1165–1171 (2016)MathSciNetCrossRefGoogle Scholar
  3. 3.
    Jia, X., Wu, G., Xie, X.: A high-performance accelerator for floating-point matrix multiplication. In: 2017 IEEE International Symposium on Parallel and Distributed Processing with Applications and 2017 IEEE International Conference on Ubiquitous Computing and Communications (ISPA/IUCC), pp. 396–402. IEEE, Dec 2017Google Scholar
  4. 4.
    Wahba, A.A., Fahmy, H.A.: Area efficient and fast combined binary/decimal floating point fused multiply add unit. IEEE Trans. Comput. 66(2), 226–239 (2017)MathSciNetzbMATHGoogle Scholar
  5. 5.
    Maan, M., Bindal, A.: A Review on IEEE-754 Standard Floating Point Arithmetic Unit (2016)Google Scholar
  6. 6.
    Ibrahimy, M.I.: FPGA implementation of multiplier for floating-point numbers based on IEEE 754-2008 standard. J. Commun. Technol. Electr. Comput. Sci. 1, 1–6 (2015)CrossRefGoogle Scholar
  7. 7.
    Sharma, B., Bakshi, A.: Design and implementation of an efficient single precision floating point multiplier using vedic multiplication. HCTL Open Int. J. Technol. Innov. Res. (IJTIR) 14, 1814–2321 (2015)Google Scholar
  8. 8.
    Lavanya, I.M., Sekhar, A.G.: FPGA Implementation of Single Precision Floating Point Multiplier using High-Speed Compressors (2018)Google Scholar
  9. 9.
    Sunesh, N.V., Sathishkumar, P.: Design and implementation of a fast floating point multiplier unit. In: 2015 International Conference on VLSI Systems, Architecture, Technology, and Applications (VLSI-SATA), pp. 1–5. IEEE, Jan 2015Google Scholar
  10. 10.
    Jia, X., Wu, G. Xie, X.: A high-performance accelerator for floating-point matrix multiplication. In: 2017 IEEE International Symposium on Parallel and Distributed Processing with Applications and 2017 IEEE International Conference on Ubiquitous Computing and Communications (ISPA/IUCC), pp. 396–402. IEEE, Dec 2017Google Scholar
  11. 11.
    Zuras, D., Cowlishaw, M., Aiken, A., Applegate, M., Bailey, D., Bass, S., Bhandarkar, D., Bhat, M., Bindel, D., Boldo, S., Canon, S.: IEEE standard for floating-point arithmetic. IEEE Std 754, 1–70 (2008)Google Scholar
  12. 12.
    Xilinx Inc.: Virtex-5 FPGA Data Sheet: DC and Switching Characteristics (DS202), v5.3, 5th edn, May 2010Google Scholar
  13. 13.
    Gao, S., Al-Khalili, D., Langlois, J.P., Chabini, N.: Decimal floating-point multiplier with binary-decimal compression based fixed-point multiplier. In: 2017 IEEE 30th Canadian Conference on Electrical and Computer Engineering (CCECE), pp. 1–6. IEEE, Apr 2017Google Scholar
  14. 14.
    Pattimi, H., Mallavarapu, R.: Pipeline decimal multiplier using binary multipliers. In: Proceedings of 2nd International Conference on Micro-Electronics, Electromagnetics and Telecommunications, pp. 211–219. Springer, Singapore (2018)Google Scholar
  15. 15.
    Véstias, M., Neto, H.: Improving the area of fast parallel decimal multipliers. Microprocess. Microsyst. 61, 96–107 (2018)CrossRefGoogle Scholar

Copyright information

© Springer Nature Singapore Pte Ltd. 2020

Authors and Affiliations

  • Shoaib Arif Shaikh
    • 1
    Email author
  • B. B. Godbole
    • 2
  • Ulhas D. Shiurkar
    • 3
  1. 1.Dr. B.A.M. UniversityAurangabadIndia
  2. 2.K.B.P.C.O.ESataraIndia
  3. 3.Deogiri Institute of Engineering and Management StudiesAurangabadIndia

Personalised recommendations