IEEE 754-Based Single- and Double-Precision Floating-Point Multiplier Analysis
In signal processing applications decimal and floating-point arithmetic units are of prominent importance. IEEE has developed the IEEE 754 standard for floating-point calculations. A revised standard IEEE 754r comes in 2008 for floating-point arithmetic units. Different conditions incorporated into the IEEE 754r have originated the novel IEEE 754-2008 standard (Eisen et al. in IBM J Res Dev 51(6):1–21, 2007) . A vital operation in calculations of DFP is the multiplication due to its wide range of uses therefore in current years several decimal multiplication designs in fixed and floating-point have been proposed with different results maintaining a compromise between parameters such as latency and area. Hence studying and proposing innovative multiplication alternatives in DFP format is attractive to find suitable design compromises. This paper presents a general approach to floating-point decimal numbers that are represented in the IEEE 754-2008 standard. For FPGA implementation the Verilog code is developed and synthesized in Xilinx Virtex 4 and 7 series for DFP multiplier.
KeywordsFloating point IEEE 754-2008 DFP FPGA etc.
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