Multilevel MPSoC Performance Evaluation, ISS Model with Timing and Priority Management

  • Abdelhakim AlaliEmail author
  • Ismail Assayad
  • Mohamed Sadik
Conference paper
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 366)


To deploy the enormous hardware resources available in Multi-Processor Systems-on-Chip (MPSoC) efficiently, rapidly and accurately, methods of Design Space Exploration (DSE) are needed to evaluate several design choices. In this article, we provide a framework that makes fast simulation and performance evaluation of MPSoC early in flow of design, therefore reducing the time of design. In this platform and within the Transaction Level Modeling (TLM) approach, we present a new definition of ISS level by introducing two complementary modeling ISST and ISSPT sublevels. This later, that we illustrate an arbiter modeling approach that allows a high performance MPSoC communication. A round-robin method is chosen for algorithm arbiter modeling because it is simple, minimizes the communication latency and has an accepted speed-up. Two applications are tested and used to validate our platform: Game of life and JPEG Encoder.

The performance of the proposed approach has been analyzed in MPSoC platform based on multi-MicroBlaze. Results of simulation show with ISSPT sublevels gives a high simulation speedup factor of up to 32 with a negligible performance estimation error margin.


Embedded multiprocessor systems Estimation of performance MPSoC TLM SystemC ISS CABA Priority management 


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    Benini, L., et al.: MPARM: Exploring the Multi-Processor SoC Design Space with SystemC. J. of VLSI Signal Processing (2005)Google Scholar
  2. 2.
    Ghenassia, F.: TLM with SystemC Concepts and Applications for Embedded Systems. Springer (2005)Google Scholar
  3. 3.
    Huang, C.-Y., et al.: SoC HW/SW verification and validation. In: 2011 16th Asia and South Pacific Design Automation Conference (ASP-DAC) (2011)Google Scholar
  4. 4.
    Hines, K., Borriello, G.: Dynamic communication models in embedded system co-simulation. In: Proceedings of the 34th Design Automation Conference (DAC 1997), Anaheim, Calif, USA, pp. 395–400 (1997)Google Scholar
  5. 5.
  6. 6.
  7. 7.
    Ventroux, N., et al.: SESAM/Par4All: a tool for joint exploration of MPSoC archi-tectures and dynamic dataflow code generation. In: Proceedings of the 2012 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools. ACM (2012)Google Scholar
  8. 8.
    Boukhechem, S., Bourennane, E.B.: TLM platform based on systemC for STARSoC design space exploration. In: AHS 2008. NASA/ESA Conference on Adaptive Hardware and Systems, Noordwijk (2008)Google Scholar
  9. 9.
    Helmstetter, C., Joloboff, V.: SimSoC: a SystemC TLM integrated ISS for full system simu-lation. In: APCCAS 2008, Macao, China (2008)Google Scholar
  10. 10.
    Gajski, D., et al.: SpecC: Specification Language and Methodology. Kluwer (2000)Google Scholar
  11. 11.
    Donlin, A.: Transaction level: flows and use models. In: CODES+ISSS 2004, Stockholm, Sweden (2004)Google Scholar
  12. 12.
    Cai, L., et al.: Transaction level modeling: an overview. In: CODES+ISSS 2003, New York, USA (2003)Google Scholar
  13. 13.
    Benini, L., et al.: SystemC cosimulation and emulation of multiprocessor SoC designs. IEEE Computer 36(4) (2003)Google Scholar
  14. 14.
    Viaud, E., Pecheux, F., Greiner, A.: An efficient TLM/T modeling and simulation environment based on parallel discrete event principles. In: DATE 2006, Munich, Germany (2006)Google Scholar
  15. 15.
    Stattelmann, S., Bringmann, O., Rosenstiel, W.: Fast and accurate source-level simulation of software timing considering complex code optimizations. In: Proceedings of the 48th Design Automation Conference. ACM (2011)Google Scholar
  16. 16.
    MicroBlaze Processor v5.4. Reference Guide, UG081 (v5.4) (2014)Google Scholar
  17. 17.
    On-Chip Peripheral Bus Architecture Specifications V2.1Google Scholar
  18. 18.
  19. 19.
    Alali, A., Assayad, I., Sadik, M.: Modeling and simulation of multiprocessor systems MPSoC by SystemC/TLM2. International Journal of Computer Science Issues (IJCSI) 11(3) (2014)Google Scholar
  20. 20.
    Sgroi, M., Lavagno, L., Sangiovanni-Vincentelli, A.: Formal Models for Embedded System Design. IEEE Design and Test of Computers 17(2), 14–27 (2000)CrossRefGoogle Scholar
  21. 21.
    Lavagno, L., Sangiovanni-Vincentelli, A., Sentovich, E.: System-level synthesis, chapter Models of computation for embedded system design, pp. 45–102. Kluwer Academic Publishers (1999)Google Scholar

Copyright information

© Springer Science+Business Media Singapore 2016

Open Access This chapter is licensed under the terms of the Creative Commons Attribution-NonCommercial 2.5 International License (, which permits any noncommercial use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license and indicate if changes were made.

The images or other third party material in this chapter are included in the chapter's Creative Commons license, unless indicated otherwise in a credit line to the material. If material is not included in the chapter's Creative Commons license and your intended use is not permitted by statutory regulation or exceeds the permitted use, you will need to obtain permission directly from the copyright holder.

Authors and Affiliations

  • Abdelhakim Alali
    • 1
    Email author
  • Ismail Assayad
    • 1
  • Mohamed Sadik
    • 1
  1. 1.Ecole Nationale Supérieure d’Electricité et de Mécanique, RTSE TeamHASSAN II UniversityCasablancaMorocco

Personalised recommendations