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3D Packaging Architectures and Assembly Process Design

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3D Microelectronic Packaging

Part of the book series: Springer Series in Advanced Microelectronics ((MICROELECTR.,volume 64))

Abstract

In this chapter, the advantages and limitations of 3D architectures are discussed to provide context for why 3D stacking is a key area of interest for product architects, why it has generated broad industry attention, and why it is seeing increased adoption in recent years (https://www.anandtech.com/tag/hbm2 [1; https://newsroom.intel.com/wp-content/uploads/sites/11/2019/08/Intel-Lakefield-HotChips-presentation.pdf [2]; Ingerly et al., IEDM [3]; Elsherbini et al., IEDM 4]). The primary focus of this chapter is on 3D architectures that use Through Silicon Vias (TSVs). The key elements of a TSV based 3D architecture are described, followed by a description of the three methods of manufacturing wafers with TSVs (i.e. Via-First, Via-Middle and Via-Last). An analysis of the different assembly process flows for 3D structures, broadly classified as (1) Wafer-to-Wafer (W2W) (2) Die-to-Wafer (D2W) and (c) Die-to-Die (D2D) assembly processes, is covered. Key design, assembly process, test process and materials considerations for each of these flows are described. The chapter concludes with a discussion of current and anticipated challenges for 3D architectures.

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Notes

  1. 1.

    Heterogeneous Integration refers to the integration of separately manufactured components (e.g. individual die, MEMS device, passive component, pre-packaged devices etc.) into a higher level assembly (SiP) that, in the aggregate, provides enhanced functionality and improved operating characteristics [7].

    SIP is considered to be sub-set of the broader concept of System on Package (SOP) [8] where an entire computer system is built on a package.

  2. 2.

    An IP (Intellectual Property) block is reusable circuit block that performs a certain specialized functions and serves as a building block for constructing the SOC.

  3. 3.

    Physical and electrical interconnect characteristics have a significant impact on chip performance [18,19,20].

  4. 4.

    In most applications Thermo-compression Bonding (TCB), is used to create the fine pitch interconnect typically needed between two stacked die, because of its superior alignment capability over reflow based flip-chip bonding [23].

  5. 5.

    WIO i.e. Wide IO is a JEDEC standard memory where the memory die are connected by TSVs [43].

  6. 6.

    Power efficiency quoted for the ESD case. See [44] for a detailed review of power and performance differences between LPDDR and Wide-IO.

  7. 7.

    It is relevant to note that [45] also includes the case of monolithic 3-D ICs where multiple devices levels are stacked within the wafer. This case is truly a bounding case of 3D integration but beyond the scope of the current chapter. References [46, 47] covers this subject in more detail.

  8. 8.

    The 2.5D nomenclature is used here to maintain consistency with literature published before 2019 HIR [7].

  9. 9.

    In reality, there will be thermal cross-talk through the heat spreader and this will affect the TDP envelope.

  10. 10.

    System cooling refers to the cooling solution attached to the SIP.

  11. 11.

    200 °C quoted as a typical lower temperature bound. A number of FEOL and MEOL processes have deposition temperatures significantly higher than 200 °C.

  12. 12.

    Descriptions in Fig. 2.11 show high level conceptual flows and specifics can vary e.g. in a Via Middle process partial metallization can precede TSV formation.

  13. 13.

    While this statement seems intuitively feasible, the authors are not aware of an authoritative study that establishes the design advantages of the Via First process over the Via Middle or Via Last options.

  14. 14.

    Note that die stacks can also be attached to the wafer and HBM stacks are a good example of this case.

  15. 15.

    It should be pointed out that this model while illustrative is simplistic in a number of ways. In real life situations, the number of process steps is higher than n; individual process step yields vary and are not always independent of each other.

  16. 16.

    In industry parlance, the acronym KGD (Known Good Die) is used to describe working die, pre-tested before package assembly.

  17. 17.

    Determining viability for assembly requires a careful optimization of cost (i.e. cost of probing die on a wafer needs to be balanced against the cost of package waste and need for additional test steps later in the flow) and test coverage (while checking a greater degree of die functionality before packaging is financially viable it can also require more sophisticated Sort technology).

  18. 18.

    One of the key considerations in manufacturing costs is the time it takes to test units. Greater the amount of time, lower the through-put and hence higher the costs. The goal in E-Test, Sort, and Package Level Test steps is to focus on test time minimization without impacting quality. Burn-in processes on the other hand are designed to run longer so that latent defects are screened out.

Abbreviations

3D:

Three Dimensional

2D:

Two Dimensional

SBS:

Side by Side

SIP:

System in Package

SOC:

System on Chip

IP:

Intellectual Property

MCP:

Multi Chip Package

MCM:

Multi Chip Module

MPM:

Multi Package Module

EMIB:

Embedded Multi-Die Interconnect Bridge

TSV:

Through Silicon Via

W2W:

Wafer to Wafer

D2W:

Die to Wafer

D2D:

Die to Die

BI:

Burn-In

Tx:

Transmitter

Rx:

Receiver

TDP:

Thermal Design Power

TIM:

Thermal Interface Material

KOZ:

Keep Out Zone

CMP:

Chemical Mechanical Polishing

ECD:

Electro Chemical Deposition

PECVD:

Plasma Enhanced Chemical Vapor Deposition

PVD:

Plasma Vapor Deposition

FEOL:

Front End of Line

MEOL:

Middle End of Line

BEOL:

Back End of Line

KGD:

Known Good Die

PCH:

Peripheral Controller Hub

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Acknowledgements

The authors would like to acknowledge Prismark Partners LLC, TechSearch International Inc, and Yole Développement for their generous permission to use their pictures. Thanks are due to Dr. Zhiguo Qian (Intel Corporation) for his help on the section on IO power dissipation, Dr. Chandra Mohan Jha (Intel Corporation) for help with thermal analysis, Professor Paul Franzon (North Carolina State University) for help getting updated latency and energy comparisons Debendra Mallik for help on the figures, Sriram Srinivasan for thorough review of the chapter and Tom DeBonis for his help in facilitating information collection. Guidance from Chris Nelson (Intel Corporation) on test processes is also gratefully acknowledged. The editors would like to thank Zhiheng Huang from Sun Yat-sen University for his critical review of this chapter.

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Authors and Affiliations

  1. Intel Fellow, High Density Interconnect Pathfinding, Assembly Technology, Intel Corporation, MS CH5-157, 5000 West Chandler Blvd, Chandler, AZ, 85226, USA

    Ravi Mahajan

  2. Retired Intel Fellow, High Density Interconnect Pathfinding, Assembly Technology, Intel Corporation, MS CH5-157, 5000 West Chandler Blvd, Chandler, AZ, 85226, USA

    Bob Sankman

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Correspondence to Ravi Mahajan .

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  1. Intel Corporation, Chandler, AZ, USA

    Yan Li

  2. Intel Corporation, Chandler, AZ, USA

    Deepak Goyal

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Mahajan, R., Sankman, B. (2021). 3D Packaging Architectures and Assembly Process Design. In: Li, Y., Goyal, D. (eds) 3D Microelectronic Packaging. Springer Series in Advanced Microelectronics, vol 64. Springer, Singapore. https://doi.org/10.1007/978-981-15-7090-2_2

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