Abstract
In this paper, analytical comparison of full adders has been presented on the basis of power, delay and PDP. All simulations are performed using SPICE in 32 nm CMOS technology. Full adder is the basic block of an arithmetic logic unit (ALU) so the power consumption and delay of an ALU are reduced by optimizing full adder. Simulation results show that for input to output carry FA-Tung has the highest speed and the lowest PDP. While for input to output sum, FA-Goel has the highest speed and the lowest PDP. FA-Conventional has the highest power consumption while FA-Tung has the lowest power consumption. For multi-bit adders, FA-Tung has the best performance.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
A.M. Shams, M. Bayoumi, Performance evaluation of 1-bit CMOS adder cells. in Proceedings of IEEE ISCAS, Orlando, FL, (vol. 1, 1999), pp. 27–30
Q.A. Al-Haija, H. Al-Amri, M. Al-Nashri, S. Al-Muhaisen, C of 4-bit special purpose microprogrammed processor, in The 4th International Conference on Emerging Ubiquitous Systems and Pervasive Networks (EUSPN-2013), Elsevier Procedia Computer Science (vol. 21, 2013), pp. 512–516
S. Parmar, K.P. Singh, Design of high speed hybrid carry select adder, in 3rd IEEE International Advance Computing Conference (IACC), Ghaziabad (2013), pp. 1656–1663
M.M. Mano, M.D. Ciletti, Digital Design, 5th edn. (Pearson Education, 2012)
J.-F. Lin, Y.-T. Hwang, M.-H. Sheu, C.-C. Ho, A novel high speed and energy efficient 10-transistor full adder design. IEEE Trans. Circuits Syst. I 54(5), 1050–1059 (2007)
Y. Jiang, A. Al-Sheraidah, Y. Wang, E. Sha, J.G. Chung, A novel multiplexer-based low-power full adder. IEEE Trans. Circuits Syst. II. Analog Digit. Signal Process 51, 345–348 (2004)
H.T. Bui, Y. Wang, Y. Jiang, Design and analysis of low-power 10-transistor full adders using XOR XNOR gates. IEEE Trans. Circuits Syst. II, Analog and Digital Signal Processing 49(1), 25–30 (2002)
D. Wang, M. Yang, W. Cheng, X. Guan, Z. Zhu, Y. Yang, Novel low power full adder cells in 180 nm CMOS technology, in 4th IEEE Conference on Industrial Electronics and Applications (2009), pp. 430–433
C.K. Tung, S.H. Shieh, C.H. Cheng, A regularly modularized multiplexer-based full adder for arithmetic applications. Appl. Math. Inf. Sci. Int. J. 8(3), 1257–1265 (2014)
S. Goel, A. Kumar, M.A. Bayoumi, Design of robust, energy-efficient full adders for deep-submicrometer design using hybrid-CMOS logic style. IEEE Trans. Very Large Scale Integr. VLSI Syst. 14, 1309–1321 (2006)
M.A. Hernandez, M.L. Aranda, CMOS full-adders for energy-efficient arithmetic applications. IEEE Trans. Very Large Scale Integr. VLSI Syst. 19(4), 718–721 (2011)
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2020 Springer Nature Singapore Pte Ltd.
About this paper
Cite this paper
Ahmed Khan, I., Rashid Mahmood, M., Keshari, J.P. (2020). Analytical Comparison of Power Efficient and High Performance Adders at 32 nm Technology. In: Saini, H.S., Singh, R.K., Tariq Beg, M., Sahambi, J.S. (eds) Innovations in Electronics and Communication Engineering. Lecture Notes in Networks and Systems, vol 107. Springer, Singapore. https://doi.org/10.1007/978-981-15-3172-9_62
Download citation
DOI: https://doi.org/10.1007/978-981-15-3172-9_62
Published:
Publisher Name: Springer, Singapore
Print ISBN: 978-981-15-3171-2
Online ISBN: 978-981-15-3172-9
eBook Packages: EngineeringEngineering (R0)