Enhancing Multi-level Cache Performance Using Dynamic R-F Characteristics

  • Akshay Motwani
  • Debabrata SwainEmail author
  • Nikhil Motwani
  • Vinit Vijan
  • Akshar Awari
  • Banchhanidhi Dash
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 1101)


Cache memory or CPU memory is a high-speed static random access memory that a computer microprocessor can access more quickly than it can access regular random access memory. Hence, the high-performance cache memory is used to bridge the performance gap between the processor and main memory. Multi-level caches refer to a type of memory hierarchy which uses memory stores with different access speed to cache data. Our proposed work uses combination of different tuning algorithms considering the R-F characteristics of page to provide an efficient solution for cache replacement in multi-level cache hierarchy which has an easy implementation and a better performance compared to traditional cache replacement policies like clock with adaptive replacement (CAR), least recently used (LRU), and first in, first out (FIFO) on a cache of equivalent size.


Clock with adaptive replacement (CAR) Least recently used (LRU) First in, first out (FIFO) Classical weight ranking policy (CWRP) 


  1. 1.
    Tanenbaum, A., and A. Woodhull. 1997. Operating systems: Design and implementation. Prentice Hall 3: 373–410.Google Scholar
  2. 2.
    Yang, Q., H. Zhang, and H. Zhang. 2001. Taylor series prediction: A cache replacement policy based on second-order trend analysis. In: Proceedings of 34th Hawaii Conference on System Science 5: 5023.Google Scholar
  3. 3.
    Belady, A. 1966. A study of replacement algorithms for a virtual storage computer. IBM systems Journal 5 (2): 78–101.CrossRefGoogle Scholar
  4. 4.
    O’Neil, E., P. O’Neil, and G. Weikum. 1999. An optimality proof of the lru-k page replacement algorithm. Journal of the ACM 46 (1): 92–112.MathSciNetCrossRefGoogle Scholar
  5. 5.
    Jihang, S., and X. Zhang. 2002. LIRS: An efficient low inter reference recency set replacement policy to improve buffer cache performance. In: Proceedings of ACM Sigmetrics Conference on ACM Presentation 2: 31–42.Google Scholar
  6. 6.
    Hosseini-khayat, S. 2000. On optimal replacement of nonuniform cache objects. IEEE Transactions on Computers 49: (8).Google Scholar
  7. 7.
    Glass, G., and P. Cao. 2003. Adaptive page replacement based on memory reference behavior. In: Proceedings of ACM SIGMETRICS Conference on Overhead Replacement Cache. Proceedings of Usenix Conference on File and Storage Technologies (FAST 2003), Usenix, 115–130.Google Scholar
  8. 8.
    Irani, S. 1997. Page replacement with multi-size pages and applications to WebCaching. In: Proceedings of 29th Annual ACM Symposium of Theory of Computing 50: 701–710.Google Scholar
  9. 9.
    Swain. D., S. Marar, N. Motwani, V. Hiwarkar, and N. Valakunde. 2017. CWRP: An efficient and classical weight ranking ploicy for enhancing cache performance. In: IEEE Fourth International Conference on Image Information Processing.Google Scholar
  10. 10.
    Swain, Debabala, Bijay Paikaray, and Swain Debabrata. 2011. AWRP: Adaptive weight ranking policy for improving cache performance. Journal of Computing 3: (2).Google Scholar
  11. 11.
    Dash, B., D. Swain, BK. Paikaray. (2017) International Journal of Computational Systems Engineering (IJCSYSE) 3: (1/2).Google Scholar
  12. 12.
    Bansal, Sorav, and Dharmendra Modha. 2004. CAR: Clock with adaptive replacement. In: USENIX File and Storage Technologies (FAST), Mar 31–Apr 2, San Francisco, CA.Google Scholar
  13. 13.
    Swain, Debabrata, Bancha Nidhi Dash, Debendra O Shamkuwar, Debabala Swain. 2012. Analysis and predictability of page replacement techniques towards optimized performance. International Journal of Computer Application Proceedings on ICRTITCS-2011 12–16.Google Scholar
  14. 14.
    Megiddo, N., and D. Modha. 2003. ARC: A self-tunning, low overhead replacement cache. In: Proceedings of Usenix Conference on File and Storage Technologies (FAST 2003). Usenix, 2: 115–130.Google Scholar

Copyright information

© Springer Nature Singapore Pte Ltd. 2020

Authors and Affiliations

  • Akshay Motwani
    • 1
  • Debabrata Swain
    • 2
    Email author
  • Nikhil Motwani
    • 1
  • Vinit Vijan
    • 1
  • Akshar Awari
    • 1
  • Banchhanidhi Dash
    • 3
  1. 1.Department of Computer EngineeringVishwakarma Institute of TechnologyPuneIndia
  2. 2.Information Technology DepartmentVishwakarma Institute of TechnologyPuneIndia
  3. 3.School of Computer EngineeringK.I.I.T. UniversityBhubaneswarIndia

Personalised recommendations