The Implementation of a Configurable MBIST Controller for Multi-core SoC

  • Chunmei HuEmail author
  • Xiaoxuan Li
  • Zhigang Fu
  • Qianqian Tang
  • Rong Zhao
Conference paper
Part of the Communications in Computer and Information Science book series (CCIS, volume 1146)


Aiming at the problem of memory test power caused by the increasing proportion of embedded memory in multi-core SoC, this paper analyzes the existing issue and proposes a configurable MBIST controller to reduce test power consumption. This paper adopts MBIST configuration scan-chain to organize test groups and adopts a configurable PLL scan-chain to drive memories to its working frequency. Clock optimization method is also adopted to reduce test power. The method proposed has the advantages of low test power, flexible test configuration and less hardware added. The method can also diagnose the site of failing memories. The actual testing of the multi-core SoC on ATE V93000 shows that the proposed method effectively reduces power consumption, and meets the requirement of memory test.


MBIST Group test Scan chain Test power consumption ATE test 


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Copyright information

© Springer Nature Singapore Pte Ltd. 2019

Authors and Affiliations

  • Chunmei Hu
    • 1
    Email author
  • Xiaoxuan Li
    • 2
  • Zhigang Fu
    • 1
  • Qianqian Tang
    • 1
  • Rong Zhao
    • 1
  1. 1.School of ComputerNational University of Defense TechnologyChangshaP.R. China
  2. 2.Xidian UniversityXianP.R. China

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