A Coherent and Power-Efficient Optical Memory Access Network for Kilo-Core Processor

  • Quanyou FengEmail author
  • Junhui Wang
  • Hongwei Zhou
  • Wenhua Dou
Conference paper
Part of the Communications in Computer and Information Science book series (CCIS, volume 1146)


Coherent and power-efficient processor-memory interconnects are of great importance for kilo-core processor design. This paper proposes a hybrid photonic architecture for such interconnection. Specifically, a bandwidth-efficient photonic network which also supports coherence management is used for memory accesses between last-level HBM caches and off-chip HMC memory pools. Simulation results show that the hybrid network achieves up to 11% of system speedup and up to 6 times of energy savings, when compared to conventional electric interconnects.


Photonic Noc HMC Memory subsystem Coherence 



This work is supported by the National Natural Science Foundation of China under Grant 61402502, Grant 61402497 and Grant 61472432, and in part by HGJ under Grant 2018ZX01029-103.


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Copyright information

© Springer Nature Singapore Pte Ltd. 2019

Authors and Affiliations

  • Quanyou Feng
    • 1
    Email author
  • Junhui Wang
    • 1
  • Hongwei Zhou
    • 1
  • Wenhua Dou
    • 1
  1. 1.National University of Defense TechnologyChangshaChina

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