Workload Aware Dynamic Scheduling Algorithm for Multi-core Systems

  • Savita Gautam
  • Abdus Samad
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 1097)


The key challenge of scheduling in multi-core systems is to map highly irregular processes that require the inspection of thread behavior and efficiency of multi-core systems. The motive is to schedule multiple tasks on multiple cores. In this paper, a novel scheduling technique is proposed that works on execution technique for tree type tasks structures that are mapped on different multi-core systems designed using different multiprocessor systems. In particular, the performance is evaluated by applying the proposed technique to a particular class of multiprocessor system known as hybrid multiprocessor systems that are used as basic building blocks of a multi-core system. The scheduling algorithm is applied by dividing tasks in terms of computation efficiency of these systems. The key novelty of the proposed method is that tasks which are executed partially may be migrated on systems which are under-loaded and having good efficiency. In other words, the scheduling of tasks to cores must be automated to adapt to the changing program behavior and current load on the system. Before migration of remaining tasks, the efficiency of core on such systems is evaluated. A comparative study is carried out by applying other standard scheduling algorithms on the same multi-core systems. Simulation results show that the proposed algorithm gives better performance while executing tasks on various multi-core systems having different computational efficiency. In particular, the load imbalance is improved by 20–30% and execution time is reduced by 35–55% as compared to traditional algorithms. Further, we show that in many cases, our approach is able to deliver better performance by combining it with classical scheduling algorithms.


Multi-core systems Scheduling algorithm Computational capability Load imbalance Execution time Performance parameter Multiprocessor interconnection networks Packet size 


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Copyright information

© Springer Nature Singapore Pte Ltd. 2020

Authors and Affiliations

  • Savita Gautam
    • 1
  • Abdus Samad
    • 1
  1. 1.F/O Engineering & Technology, University Women’s Polytechnic, Aligarh Muslim UniversityAligarhIndia

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