Low-Power 8-Bit Adiabatic Barrel Shifter for DSP Applications

  • Nagesh NazareEmail author
  • B. S. Premananda
  • Pradeep S. Bhat
  • R. J. Nayana
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 1089)


The CMOS technology is recognized for high levels of integration and low power dissipation. Portable devices usually operate on batteries with minimal charge storage capacity. Power consumption is the limiting factor for the functionality offered by portable devices that operate on batteries. This has made researchers explore for new techniques to recover the energy from the circuit. One of the efficient ways to reduce the power consumption of the circuits is to design the circuit using adiabatic logic. Shifters are one of the basic elements of digital signal processors and are used for manipulating the data. Shifters are used to efficiently perform division and multiplication operation on unsigned integers by powers of two. There exist two types of shifters, viz. combinational and sequential Shifters. The paper focuses on the design of power efficient 8-bit combinational shifter, namely barrel shifter using positive feedback adiabatic logic (PFAL). Also, a comparison is performed with the conventional static CMOS barrel shifter using multiplexer logic and pass transistor logic. Cadence Virtuoso is used for the implementation with CMOS 180 nm technology, and Cadence Spectre simulator is used for simulation and functional verification. The analysis of the logic circuits infers that PFAL-based barrel shifter consumes the least power. The power values infers that PFAL technique is advantageous when applied to low-power digital devices operated at relatively low frequencies.


Adiabatic logic Barrel shifter DSP Spectre PFAL 


  1. 1.
    Bhati, P., Rizvi, N.Z.: Adiabatic logic: an alternative approach to low power application circuits. In: The Proceedings of IEEE International Conference on Electrical, Electronics, and Optimization Techniques, Chennai, vol. 1, pp. 4255–4260 (2016)Google Scholar
  2. 2.
    Teichmann, P.: Introduction to Adiabatic logic. Springer Series in Advanced Microelectronics, vol. 34. Springer, Dordrecht (2012)Google Scholar
  3. 3.
    Sivakumar, R., Jothi, D.: Recent trends in low power VLSI design. Int. J. Comput. Electr. Eng. 6, 509–523 (2014)CrossRefGoogle Scholar
  4. 4.
    Goyal, S., Singh, G., Sharma, P.: Variation of power dissipation for Adiabatic CMOS and conventional CMOS digital circuits. In: The Proceedings of 2nd IEEE International Conference on Electronics and Communication Systems, vol. 2, pp. 162–166 (2015)Google Scholar
  5. 5.
    Teichmann, P.: Fundamentals of Adiabatic logic. Springer Series in Advanced Microelectronics, vol. 34. Springer, Dordrecht (2012)Google Scholar
  6. 6.
    Verma, R., Mehra, R.: Area efficient layout design analysis of CMOS Barrel Shifter. Int. J. Sci. Res. Eng. Technol. 84–89 (2015)Google Scholar
  7. 7.
    Yedidya, H., Lee, R.B.: A new basis for shifters in general-purpose processors for existing and advanced bit manipulations. IEEE Trans. Comput. 58, 1035–1104 (2009)MathSciNetCrossRefGoogle Scholar
  8. 8.
    Premananda, B.S., Chandana, M.K., Shree Lakshmi, K.P., Keerthi, A.M.: Design of low power 8-bit carry-select adder using Adiabatic logic. In: The Proceedings of IEEE International Conference on Communication and Signal Processing, pp. 1764–1768 (2017)Google Scholar
  9. 9.
    Nazare, N., Bhat, P.S., Jambhe, N.R., Premananda, B.S.: Design and analysis of 16-bit parallel-prefix Adiabatic adders. In: The Proceeding of 3rd IEEE International Conference on Recent Trends in Electronics, Information and Communication Technology, Bengaluru (2018)Google Scholar
  10. 10.
    Anantharaman, K., Manikandan, A.V.M.: Adiabatic techniques for energy-efficient Barrel Shifter design. In: VLSI Design: Circuits, Systems and Applications. Lecture Notes in Electrical Engineering, vol. 469. Springer (2018)Google Scholar
  11. 11.
    Tatajee, D.A., Rajesh, K.: Semi-custom implementation of area efficient Barrel shifter. Int. J. Adv. Comput. Eng. Appl. 1, 112–114 (2012)Google Scholar
  12. 12.
    Nikhil, G.V., Vaibhav, B.P., Naik, V.G., Premananda, B.S.: Design of low power Barrel Shifter and Vedic-Multiplier with Kogge-Stone adder using reversible logic gates. In: The Proceedings of IEEE International Conference on Communication and Signal Processing, pp. 1690–1694 (2017)Google Scholar
  13. 13.
    Singh, R., Rajesh, M.: Power efficient design of Multiplexer using Adiabatic logic. Int. J. Adv. Eng. Technol. 6, 246–254 (2013)Google Scholar

Copyright information

© Springer Nature Singapore Pte Ltd. 2020

Authors and Affiliations

  • Nagesh Nazare
    • 1
    Email author
  • B. S. Premananda
    • 1
  • Pradeep S. Bhat
    • 1
  • R. J. Nayana
    • 1
  1. 1.R.V. College of EngineeringBengaluruIndia

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