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Design of Low Power Reduced Complexity Wallace Tree Multiplier Using Positive Feedback Adiabatic Logic

  • M. G. GanaviEmail author
  • B. S. Premananda
Conference paper
  • 17 Downloads
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 1089)

Abstract

The demand for low power devices is exponentially increasing with the increase in the use of portable equipment such as laptops and mobile phones. Adiabatic logic is an emerging technique which proves to be efficient in reducing the power dissipation of the system. Positive Feedback Adiabatic Logic (PFAL) is an efficient adiabatic logic. Multipliers are the fundamental arithmetic operators in the digital circuits. Addition is the integral part of multiplication, to add the partial products. A 16-bit Wallace Tree Multiplier (WTM) is implemented using carry-save addition. The Conventional WTM (CWTM) is modified to minimize complexity, termed as Reduced Complexity WTM (RCWTM) which has minimum number of Half Adders compared to the CWTM, which results in the reduction of the WTM area. The RCWTM is designed using both static CMOS logic and PFAL. The design is analyzed in Cadence Virtuoso 180 nm technology and simulated in Cadence Spectre. The PFAL based RCWTM dissipates 81.8% less power compared to static CMOS design.

Keywords

Adiabatic Carry-save adder CMOS PFAL Wallace Tree Multiplier 

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Copyright information

© Springer Nature Singapore Pte Ltd. 2020

Authors and Affiliations

  1. 1.Department of Telecommunication EngineeringR.V. College of EngineeringBengaluruIndia

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