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Design of Low-Power Vedic Multipliers Using Pipelining Technology

  • Ansiya EshackEmail author
  • S. Krishnakumar
Conference paper
  • 15 Downloads
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 1090)

Abstract

This paper proposes a study on how pipelining technology can be used in Vedic multipliers, employing Urdhava Tiryakbhyam sutra, to increase the speed and reduce the power consumption of a system. Pipelining is one of the methods used in the design of low-power systems. Vedic multipliers use an ancient style of multiplying numbers which allows for easier and faster calculations, compared to the regular mathematical method. The concept of pipelining, when used in these multipliers, leads to a system which computes calculations faster using lesser hardware. The study includes the direct use of pipelining in 2 × 2 bit, 4 × 4 bit, 8 × 8 bit and 16 × 16 bit Vedic multipliers. The pipelining is then further incorporated at different levels to create 8 × 8 bit and 16 × 16 bit multipliers. The algorithm of the system is implemented on Spartan 3E field-programmable gate array (FPGA). The designed system uses lesser power and has lower delay compared to the existing systems.

Keywords

Pipelining FPGA Vedic mathematics Low-power Vedic multipliers Urdhava Tiryakbhyam sutra 

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Copyright information

© Springer Nature Singapore Pte Ltd. 2020

Authors and Affiliations

  1. 1.School of Technology & Applied Sciences, M. G. University Research CentreEdapally, ErnakulamIndia

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