Design of Power Efficient and High-Performance Architecture to Spectrum Sensing Applications Using Cyclostationary Feature Detection

  • Kadavergu AishwaryaEmail author
  • T. Jagannadha Swamy
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 1040)


Cognitive radio spectrum sensing is one of the novel techniques in wireless communications. In this process, a wide variety of techniques are available for detecting the spectrum availability to send the secondary signal frequency signals in the absences of the other primary signal frequencies. In this cognitive radio spectrum sensing, speed of operation of the network is one of the important factors for efficient data handling and transmission process. Cyclostationary feature detection is one of the efficient methods for Cognitive Radio spectrum sensing applications. The speed and power of the cyclostationary feature detection-based spectrum sensing architecture in cognitive radio networks can be improved by implementing the advanced multiplication techniques like Vedic multipliers for test statistic computing module deployed in the architecture. To detect the presence the signal over the provided Frequency band, continuous sensing of spectrum is required. This involves numerous multiplications. The proposed model with help of Vedic multipliers reduces the power consumption as well as increases the performance of the architecture. The simulation results are equated with Booth multiplier. It shows better results when it is implemented in the test statistic module. The complete design is implemented in Verilog and tested using Xilinx ISE and Xilinx Vivado tool.


Cognitive radio Spectrum sensing Cyclostatioary detection Test statistic module Booth multiplication technique Vedic multiplier 


  1. 1.
    Ghasemi, A., Sousa, E.S.: Spectrum sensing in cognitive radio networks requirements, challenges and design trade-offs. IEEE 46(4), 32–39 (2008)Google Scholar
  2. 2.
    Yucek, T., Arslan, H.: A survey of spectrum sensing algorithms for cognitive radio applications. IEEE Commun. Surv. Tutorials 11 (2009)CrossRefGoogle Scholar
  3. 3.
    Gardner, W.A., Franks, L.: Characterization of cyclostationary random signal processes. IEEE Trans. Inf. Theory 21(1), 4–14 (1975)CrossRefGoogle Scholar
  4. 4.
    Razhavi, B.: Cognitive radio design challenges and techniques. IEEE J. Solid-State Circ. (JSSC) 45(8), 1542–1553 (2010)CrossRefGoogle Scholar
  5. 5.
    Vijay, G., Bdira, E.B.A., Ibnkahla, M.: Cognition in wireless sensor networks: a perspective. IEEE Sensors 11(3), 582–592 (2011)CrossRefGoogle Scholar
  6. 6.
    Joshi, G.P., Nam, S.Y., Kim, S.W.: Cognitive radio wireless sensor networks: applications, challenges and research trends. Sens. 13(9), 11196–11228 (2013)CrossRefGoogle Scholar
  7. 7.
    Murthy, M.S., Shrestha, R.: VLSI architecture for cyclostationary feature detection-based spectrum sensing for cognitive-radio wireless networks and its ASIC implementation. In: IEEE Computer Society Annual Symposium on VLSI, pp. 69–74 (2016)Google Scholar
  8. 8.
    Murthy, M.S., Shrestha, R.: Reconfigurable and memory-efficient cyclostationary spectrum sensor for cognitive-radio wireless networks. IEEE (2017)Google Scholar
  9. 9.
    Chaudhari, S., Koivunen, V., Poor, V.: Autocorrelation-based decentralized sequential detection of OFDM signals in cognitive radios. IEEE Trans. Signal Process. 57(7), 2690–2700 (2009)MathSciNetCrossRefGoogle Scholar
  10. 10.
    Dandawate, A.V., Giannakis, G.B.: Statistical tests for presence of cyclostationarity. IEEE Trans. Signal Process. 42(9), 2355–2369 (1994)CrossRefGoogle Scholar
  11. 11.
    Hanumantharaju, M.C., Jayalaxmi, H., Renuka, R.K.: A high speed block convolution using ancient indian vedic mathematics. In: International Conference on Computational Intelligence and Multimedia Applications (2007)Google Scholar
  12. 12.
    Saha, P.K., Banerjee, A., Dandapat, A.: High speed low power complex multiplier design using parallel adders and subtractors. Int. J. Electron. Electr. Eng. (IJEEE) 7(II), 38–46 (2009)Google Scholar
  13. 13.
    Tiwari, H.D., Gankhuyag, G., Kim, C.M., Cho, Y.B.: Multiplier design based on ancient Indian vedic mathematics. In: International SoC Design Conference (2008)Google Scholar

Copyright information

© Springer Nature Singapore Pte Ltd. 2020

Authors and Affiliations

  1. 1.ECE DepartmentGRIETHyderabadIndia

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