Applications of Oxide-Channel Ferroelectric-Gate Thin-Film Transistors
- 59 Downloads
In this chapter, recent topics on oxide-channel ferroelectric-gate transistors were presented. First, nonvolatile memory circuit application of ferroelectric-gate transistors is discussed by comparing it with Flash memory. It is pointed out that “read disturb” may become serious in the memory circuits using ferroelectric-gate transistors in contrast to Flash memory. To solve the read disturb problem, two-transistor memory cell structures are presented for both NAND and NOR configurations. In NAND configuration, one memory cell consists of parallel connection of a memory transistor and a pass transistor, whereas one memory cell consists of series connection of a memory transistor and a cut-off transistor in NOR configuration. Next, two-transistor cell NAND memory arrays using oxide-channel ferroelectric-gate transistors for both memory and pass transistors have been fabricated. It is confirmed that the stored “off” data in unselected cells remain almost intact during the readout procedures of a selected cell. Next, solution process is demonstrated to fabricate oxide-channel ferroelectric-gate transistors. All-oxide, all-solution-processed ferroelectric-gate transistors are demonstrated. In addition, newly developed nano-rheology printing (n-RP) technology, which utilizes direct nanoimprint of oxide gel films, is used to fabricate oxide-channel ferroelectric thin-film transistors without using conventional lithography process.
The author would like to acknowledge members of JST ERATO, “Shimoda Nano-Liquid Process” project.
- 1.H. Ishiwara, M. Okuyama, Y. Arimoto (eds.), Ferroelectric Random Access Memories, Fundamentals and Applications (Springer, Berlin, 2004)Google Scholar
- 2.M. Okuyama, Y. Ishibashi (eds), Ferroelectric Thin Films, Basic Properties and Device Physics for Memory Applications (Springer, Berlin, 2005)Google Scholar
- 3.Y. Kaneko, H. Tanaka, M. Ueda, Y. Kato, E. Fujii, IEEE Trans. Electron Devices, 58, 1311 (2011)Google Scholar
- 4.H. Saiki, E. Tokumitsu, IEICE Trans. Electron. E87-C, 1700 (2004)Google Scholar
- 5.B.N.Q. Trinh, T. Miyasako, T. Kaneda, P.V. Thanh, P.T. Tue, E. Tokumitsu, T. Shimoda, in 2011 International Conference on Solid State Devices and Materials (SSDM), (Ext. Abst., Nagoya, 2011), p. 967Google Scholar
- 6.T. Miyasako, B.N.Q. Trinh, M. Onoue, T. Kaneda, P.T. Tue, E. Tokumitsu, T. Shimoda, Jpn. J. Appl. Phys., 50, 04DD09-1-6 (2011)Google Scholar
- 7.E. Tokumitsu, M. Senoo, T. Miyasako, Use of ferroelectric gate insulator for thin film transistors with ITO channel. J. Microelectr. Eng. 80, 305–308 (2005)Google Scholar
- 8.T. Miyasako, M. Senoo, E. Tokumitsu, Ferroelectric-gate thin–film transistors using indium-tin-oxide channel with large charge controllability. Appl. Phys. Lett. 86(16), 162902-1–162903 (2005)Google Scholar
- 9.T. Kaneda, D. Hirose, T. Miyasako, P.T. Tue, Y. Murakami, S. Kohara, J. Li, T. Mitani, E. Tokumitsu, T. Shimoda, J. Mater. Chem. C 2, 40–49 (2014)Google Scholar