Design of CMOS Instrumentation Amplifier Using Three-Stage Operational Amplifier for Low Power Signal Processing

  • Shubham SaurabhEmail author
  • Mujahid Saifi
  • Shylaja V. Karatangi
  • Amrita Rai
Conference paper
Part of the Algorithms for Intelligent Systems book series (AIS)


In this paper, the CMOS Instrumentation amplifier using a three-stage operational Amplifier is presented for low power applications, whose operating power supply is 3 V. The power supply is reduced to decrease the power consumption of the whole circuit. The passive-resistive loads are replaced by active load, i.e. by NMOS (in linear region behaves as a resistor) which reduces the overall chip area and contributes to lesser power dissipation. Active load, in turn, produces higher resistance values compared to passive loads thus results in higher values of power gain. Its large gain can amplify even very small signals ranging from 10−6 Vs to 10−3 Vs. In the previous studies of two-stage Op-amp when operated with resistive load at the output, the overall gain of the circuit is reduced. Also, another problem with two-stage Op-Amp is the trade-off, when we reduce the channel length for increasing speed of Op-Amp then the gain is reduced. Thus, the three-stage Op-amp is presented which can have high gain, high operating speed also when operated at the lesser supply voltage. The proposed Operational amplifier is simulated in H-spice at Level-2 (i.e. 180 nm CMOS technology) and AC analysis results of Avanwaves are shown.


Instrumentation amplifier Op-amp CMOS CMRR Power dissipation 


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Copyright information

© Springer Nature Singapore Pte Ltd. 2020

Authors and Affiliations

  • Shubham Saurabh
    • 1
    Email author
  • Mujahid Saifi
    • 1
  • Shylaja V. Karatangi
    • 1
  • Amrita Rai
    • 1
  1. 1.G.L Bajaj Institute of Technology and ManagementGreater NoidaIndia

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