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Novel Hardware Design of Correlation Function and Its Application on Binary Matrix Factorization Based Features

  • Mayank JainEmail author
  • Rahul Saini
  • Manish
  • Kriti Suneja
Conference paper
  • 42 Downloads
Part of the Algorithms for Intelligent Systems book series (AIS)

Abstract

Machine learning is being used in a wide variety of applications in our daily lives, such as image processing, speech processing, text analysis, stock market, etc. Most of these applications contain a lot of features so that features’ extraction is an important step in the process because of the huge size of raw data. Binary Matrix Factorization is a common method for extracting non-traditional features from the data to be processed. It is a powerful data mining tool. Correlation is one of the ways to check the similarity of data. In this paper, we have proposed a novel hardware design of correlation using Binary Matrix Factorization in order to increase the frequency of operation of this step in machine learning. The goal is to use it as an independent processing unit in portable embedded systems. The target device used for synthesis is xa6slx100-2-fgg484 in Xilinx and simulations were performed in ISim. Propagation delay and hardware utilization analysis has been shown to compare its efficacy with software implementation.

Keywords

Machine learning Field Programmable Gate Array (FPGA) Binary Matrix Factorization (BMF) 

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Copyright information

© Springer Nature Singapore Pte Ltd. 2020

Authors and Affiliations

  1. 1.Department of Electronics and CommunicationDelhi Technological UniversityDelhiIndia

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