Advertisement

Introduction

  • Kirti Gupta
  • Neeta Pandey
  • Maneesha Gupta
Chapter

Abstract

Digital integrated circuits have witnessed a phenomenal growth in the past few decades due to technological advancements and availability of electronic design automation tools.

References

  1. 1.
    S. Kiaei, D. Allstot, Low-noise Logic for Mixed-mode VLSI Circuits. Microelectron. J. 23(2), 103–114 (1992)CrossRefGoogle Scholar
  2. 2.
    B. Razavi, Design of Analog CMOS Integrated Circuits (Tata McGraw Hill Edition, 2007)Google Scholar
  3. 3.
    P.E. Allen, D.R. Holberg, CMOS Analog Circuit Design, 2nd edn. (Oxford University Press, 2007)Google Scholar
  4. 4.
    S.M. Kang, Y. Leblebici, CMOS Digital Integrated Circuits: Analysis and Design (Tata McGraw Hills, Third Edition, 2006Google Scholar
  5. 5.
    J.M. Rabaey, A. Chandrakasan, B. Nikolic, Digital Integrated Circuits, 2nd edn. (Pearson Education, 2003)Google Scholar
  6. 6.
    S. Kiaei, S. Chee, D. Allstot, CMOS source-coupled logic for mixed-mode VLSI, in Proceedings of IEEE International Symposium on Circuits and Systems (New Orleans, 1990), pp. 1608–1611Google Scholar
  7. 7.
    B. Stanistic, N. Verghese, R. Rutenbar, L. Carley, D. Allstot, Addressing substrate coupling in mixed-mode ICs: simulation and power distribution synthesis. IEEE J. Solid-State Circ. 29(3), 226–238 (1994)CrossRefGoogle Scholar
  8. 8.
    D. Su, M. Loinaz, S. Masui, B. Wooley, Experimental results and modeling techniques for substrate noise in mixed-signal integrated circuits. IEEE J. Solid-State Circ. 28(4), 420–430 (1993)CrossRefGoogle Scholar
  9. 9.
    S. Masui, Simulation of substrate coupling in mixed-signal MOS circuits, in Proceedings of IEEE Symposium on VLSI Circuits (Seattle, 1992), pp. 42–43Google Scholar
  10. 10.
    R. Sàez, M. Kayal, M. Declercq, M. Schneider, Digital circuit techniques for mixed analog/digital circuits applications, in Proceedings of IEEE International Conference on Electronics, Circuits and System (Rodos, 1996), pp. 956–959Google Scholar
  11. 11.
    D. Allstot, S. Chee, S. Kiaei, M. Shristawa, Folded source-coupled logic versus CMOS static logic for low-noise mixed-signal ICs. IEEE Trans. Circ. Sys. I 40(9), 553–563 (1993)CrossRefGoogle Scholar
  12. 12.
    S. Badel, in MOS Current-Mode Logic Standard Cells for High-Speed Low-Noise Applications (thesis no. 4098, 2008)Google Scholar
  13. 13.
    E. Albuquerque, J. Fernandes, M. Silva, NMOS current-balanced logic. Electron. Lett. 32(11), 997–998 (1996)CrossRefGoogle Scholar
  14. 14.
    L. Yang, J.S. Yuan, Enhanced techniques for current balanced logic in mixed-signal ICs, in Proceedings of IEEE Computer Society Annual Symposium on VLSI (2003), pp. 1–2Google Scholar
  15. 15.
    E.F.M. Albuquerque, M.M. Silva, An experimental comparison of substrate noise generated by CMOS and by low-noise digital circuit, in Proceedings of IEEE International Symposium on Circuits and Systems, (2004), pp. II-481–II-482Google Scholar
  16. 16.
    P. Saxena, K.M. Sudheer, V.B. Chandratre, Design of novel current balanced voltage controlled delay element. Int. J. VLSI Des. Commun. Syst. 5(3), 37–45 (2014)CrossRefGoogle Scholar
  17. 17.
    H. Ng, D. Allstot, CMOS current steering logic for low-voltage mixed-signal integrated circuits. IEEE Trans. VLSI Syst. 5(3), 301–308 (1997)CrossRefGoogle Scholar
  18. 18.
    S. Radiom, B. Sheikholeslami, H. Aminzadeh, R. Lotfi, Folded-current-steering DAC: an approach to low-voltage high-speed high-resolution D/A converters, in Proceedings of IEEE International Symposium on Circuits and Systems (2006), pp. 4783–4786Google Scholar
  19. 19.
    D.Y. Jeong, S.H. Chai, W.C. Song, G.H. Cho, CMOS current-controlled oscillators using multiple-feedback-loop ring architectures, in Proceedings of IEEE International Solid-state Circuits Conference (1997), pp. 386–491Google Scholar
  20. 20.
    S. Maskai, S. Kiaei, D. Allstot, Synthesis techniques for CMOS folded source-coupled logic circuits. IEEE J. Solid-State Circ. 27(8), 1157–1167 (1992)CrossRefGoogle Scholar
  21. 21.
    J. Kundan, S. Hasan, Enhanced folded source-coupled logic technique for low-voltage mixed-signal integrated circuits. IEEE Trans. Circ. Syst. II 47(8), 810–817 (2000)CrossRefGoogle Scholar
  22. 22.
    M. Maleki, S. Kiaei, Enhancement source-coupled logic for mixed-mode VLSI circuits. IEEE Trans. Circ. Syst. II 39(7), 399–402 (1992)CrossRefGoogle Scholar
  23. 23.
    M. Yamashina, H. Yamada, An MOS current mode logic (MCML) circuit for low-power sub-GHz processors. IEICE Trans. Electr. E75-C(10), 1181–1187 (1992)Google Scholar
  24. 24.
    M. Yamashina, M. Mizuno, K. Furuta, H. Igura, M. Nomura, H. Abiko, K. Okabe, A. Ono, H. Yamad, A low-supply voltage GHz MOS integrated circuit for mobile computing systems, in Proceedings of IEEE Symposium on Low Power Electronics (San Diego, 1994), pp. 80–81Google Scholar
  25. 25.
    M. Mizuno, M. Yamashina, K. Furuta, H. Igura, H. Abiko, K. Okabe, A. Ono, H. Yamada, A GHz MOS adaptive pipeline technique using MOS current-mode logic. IEEE J. Solid-State Circ. 31(6), 784–791 (1996)CrossRefGoogle Scholar
  26. 26.
    J.M. Musicer, J. Rabaey, MOS current mode logic for low power, low noise, CORDIC computation in mixed-signal environments, in Proceedings of International Symposium of Low Power Electronics and Design (2000), pp. 102–107Google Scholar
  27. 27.
    S. Bruma, Impact of on-chip process variations on MCML performance, in Proceedings of IEEE Conference on Systems-on-Chip (2003), pp. 135–140Google Scholar
  28. 28.
    M. Alioto, G. Palumbo, Design strategies for source coupled logic gates. IEEE Trans. Circ. Syst. I 50(5), 640–654 (2003)CrossRefGoogle Scholar
  29. 29.
    M. Alioto, G. Palumbo, S. Pennisi, Modelling of source-coupled logic gates. Int. J. Circ. Theory Appl. 30(4), 459–477 (2002)zbMATHCrossRefGoogle Scholar
  30. 30.
    M. Hassan, M. Anis, M. Elmasry, MOS current mode circuits: analysis, design, and variability. IEEE Trans. Very Large Scale Integr. VLSI Syst. 13(8), 885–898 (2005)CrossRefGoogle Scholar
  31. 31.
    M. Alioto, G. Palumbo, Power-delay optimization of D-latch/MUX source coupled logic gates. Int. J. Circ. Theory Appl. 33(1), 65–85 (2005)zbMATHCrossRefGoogle Scholar
  32. 32.
    M. Alioto, L. Pancioni, S. Rocchi, V. Vignoli, Analysis and design of MCML gates with hysteresis, in Proceedings of International Symposium on Circuits and Systems (Island of KOS, 2006), pp. 1263–1267Google Scholar
  33. 33.
    M. Alioto, G. Palumbo, Modelling and design considerations on CML gates under high-current effects. Int. J. Circ. Theory Appl. 33, 503–518 (2005)zbMATHCrossRefGoogle Scholar
  34. 34.
    M. Alioto, G. Palumbo, Nanometer MCML gates: models and design considerations, in Proceedings of IEEE International Symposium on Circuits and Systems (Marrakech, 2006)Google Scholar
  35. 35.
    M. Alioto, Design of nanometer MOS current mode logic: from very high-speed down to ultra-low power, in Proceedings of International Conference on Microelectronics (2009), pp. 12–13Google Scholar
  36. 36.
    M. Alioto, G. Palumbo, Model and design of bipolar and MOS current-mode logic (CML, ECL and SCL Digital Circuits) (Kluwer Academic Publications, 2005)Google Scholar
  37. 37.
    N. Pandey, K. Gupta, G. Bhatia, B. Choudhary, MOS current mode logic exclusive-OR gate using multi-threshold triple-tail cells. Microelectr. J. 57, 13–20 (2016)CrossRefGoogle Scholar
  38. 38.
    N. Pandey, M. Gupta, K. Gupta, A PFSCL based configurable logic block, in Proceedings of Annual IEEE India International Conference INDICON (2015), pp. 1–4Google Scholar
  39. 39.
    N. Pandey, K. Gupta, M. Gupta, An efficient triple-tail cell based PFSCL D-latch. Microelectr. J. 45(8), 1001–1007 (2014)CrossRefGoogle Scholar
  40. 40.
    K. Gupta, N. Pandey, M. Gupta, Analysis and design of MOS current mode logic exclusive-OR gate using triple-tail cells. Microelectr. J. 44(6), 561–567 (2013)CrossRefGoogle Scholar
  41. 41.
    K. Gupta, N. Pandey, M. Gupta, Low-voltage MOS current mode logic multiplexer. Radio Eng. 22(1), 259–268 (2013)Google Scholar
  42. 42.
    K. Gupta, N. Pandey, M. Gupta, MCML D-latch using triple-tail cells: analysis and design. Active Passive Electr. Comp. 2013, 9 (2013). (Article ID: 217674)Google Scholar
  43. 43.
    A.H. Ismail, M.I. Elmasry, A low power design approach for MOS current mode logic, in Proceedings of IEEE Conference on Systems on-Chip (2003), pp. 143–146Google Scholar
  44. 44.
    G. Caruso, Design of MOS current mode logic gates-computing the limits of voltage swing and bias current, in Proceedings of IEEE International Symposium on Circuits and Systems (2005), pp. 5637–5640Google Scholar
  45. 45.
    G. Caruso, A. Macchiarella, Optimum design of two-level MCML gates, in Proceedings of IEEE International Conference on Electronics, Circuits and Systems (St. Julien’s, 2008), pp. 141–144Google Scholar
  46. 46.
    O. Musa, M. Shams, An efficient delay model for MOS current-mode logic automated design and optimization. IEEE Trans. Circ. Syst. I 57(8), 2041–2052 (2010)MathSciNetGoogle Scholar
  47. 47.
    U. Seckin, C.K. Yang, A comprehensive delay model for CMOS CML circuits. IEEE Trans. Circ. Syst. I Regul. Papers 55(9), 2608–2618 (2010)MathSciNetCrossRefGoogle Scholar
  48. 48.
    H. Hassan, M. Anis, M. Elmasry, Design and optimization of MOS current mode logic for parameter variations. Integr. VLSI J. Special Issue: ACM Great Lakes Symp. VLSI 38(3), 417–437 (2005)CrossRefGoogle Scholar
  49. 49.
    R.P. Arroyo, P.A. Moya, H. Wolfgang, Design of a MCML gate library applying multiobjective optimization, in Proceedings of the IEEE Computer Society Annual Symposium on VLSI (Porto. Alegre, 2007), pp. 310–314Google Scholar
  50. 50.
    R. Pereira, P. Alvarado, H. Krautschneider, Multi-objective optimization of MCML circuits using a genetic algorithm, in Workshop on Iberchip In Memorias (2006), pp. 1–4Google Scholar
  51. 51.
    A. Tanabe, M. Umetani, I. Fujiwara, T. Ogura, K. Kataoka, M. Okihara, H. Sakuraba, T. Endoh, F. Masuoka, 0.18-μm CMOS 10-Gb/s multiplexer/demultiplexer ICs using current mode logic with tolerance to threshold voltage fluctuation. IEEE J. Solid-State Circ. 36(6), 988–996 (2001)CrossRefGoogle Scholar
  52. 52.
    A. Tanabe, M. Umetani, I. Fujiwara, T. Ogura, K. Kataoka, M. Okihara, H. Sakuraba, T. Endoh, F. Masuoka, A 10-Gb/s multiplexer/demultiplexer IC in 0.18 μm CMOS using current mode logic with tolerance to threshold voltage fluctuation, in Proceedings of IEEE International Conference on Solid-State Circuits (San Francisco, 2000), pp. 62–63Google Scholar
  53. 53.
    H. Hassan, M. Anis, M. Elmasry, Low power multi-threshold MCML: analysis, design and variability. Microelectron. J. 37(10), 1097–1104 (2006)CrossRefGoogle Scholar
  54. 54.
    H. Hassan, M. Anis, M. Elmasry, Analysis and design of low-power multi-threshold MCML, in Proceedings of the IEEE International Conference on System-on-Chip (2004), pp. 25–29Google Scholar
  55. 55.
    K. Zhou, S. Chen, A. Rucinski, J.F. McDonald, T. Zhang, Self-timed triple-rail MOS current mode logic pipeline for power-on-demand design, in Proceedings of IEEE International Symposium on Circuits and Systems (2005), pp. 1394–1397Google Scholar
  56. 56.
    K. Zhou, Y. Luo, S. Chen, A. Drake, J.F. McDonald, T. Zhang, Triple-rail MOS current mode logic for high-speed self-timed pipeline applications, in Proceedings of IEEE International Symposium on Circuits and Systems (Island of KOS, 2006), pp. 3654–3657Google Scholar
  57. 57.
    M. Alioto, L. Pancioni, S. Rocchi, V. Vignoli, Modeling and evaluation of positive-feedback source-coupled logic. IEEE Trans. Circ. Syst. I Regul. Papers 51(4), 2345–2355 (2004)MathSciNetzbMATHCrossRefGoogle Scholar
  58. 58.
    M. Alioto, A. Fort, L. Pancioni, S. Rocchi, V. Vignoli, Positive-feedback source-coupled logic: a delay model, in Proceedings of IEEE Symposium on Circuits and Systems (2004), pp. II/641–644Google Scholar
  59. 59.
    M. Alioto, A. Fort, L. Pancioni, S. Rocchi, V. Vignoli, An approach to the design of PFSCL gates, in Proceedings of IEEE Symposium on Circuits and Systems (2005), pp. 2437–2440Google Scholar
  60. 60.
    M. Alioto, L. Pancioni, S. Rocchi, V. Vignoli, Power-delay-area-noise margin trade-offs in positive-feedback source-coupled logic gates. IEEE Trans. Circ. Syst. I Regul. Papers 54(9), 1916–1928 (2007)CrossRefGoogle Scholar
  61. 61.
    M. Alioto, L. Pancioni, S. Rocchi, V. Vignoli, Exploiting hysteresys in MCML circuits. IEEE Trans. Circ. Syst. II 53(11), 1170–1174 (2006)CrossRefGoogle Scholar
  62. 62.
    R. Cao, J. Hu, Near-threshold computing of single-rail MOS current mode logic circuits. Res. J. Appl. Sci. Eng. Technol. 5, 2991–2996 (2013). (Article ID: 836019)CrossRefGoogle Scholar
  63. 63.
    M.P. Houlgate, D.J. Olszewski, K. Abdelhalim, L.M. Eachern, Adaptable performance MOS current mode logic for use in a 3 GHz programmable frequency divider, in Proceedings of IEEE Conference on Circuits and Systems (2003), pp. 1303–1306Google Scholar
  64. 64.
    M.P. Houlgate, D.J. Olszewski, K. Abdelhalim, L.M. Eachern, Adaptable MOS current mode logic for use in a multi-band RF prescaler, in Proceedings of IEEE Conference on Circuits and Systems (2004), pp. 329–332Google Scholar
  65. 65.
    A. Worapishet, M. Thamsirianunt, An NMOS inductive loading technique for extended operating frequency CMOS ring oscillators, in Proceedings of IEEE Midwest Symposium on Circuits and Systems (2002), pp. 116–119Google Scholar
  66. 66.
    H.T. Bui, Y. Savaria, 10 GHz PLL using active shunt-peaked MCML gates and improved frequency acquisition XOR phase detector in 0.18 μm CMOS, in Proceedings of the IEEE International Workshop SOC for Real-Time Applications (2004), pp. 115–118Google Scholar
  67. 67.
    S.S. Mohan, M.del Mar Hershenson, S.P. Boyd, T.H. Lee, Bandwidth extension in CMOS with optimized on-chip inductors. IEEE J. Solid-State Circ. 35(3), 346–354 (2000)CrossRefGoogle Scholar
  68. 68.
    H.T. Bui, Y. Savaria, Shunt-peaking of MCML gates using active inductors, in Proceedings of IEEE Northeast Workshop on Circuits and Systems (2004), pp. 361–364Google Scholar
  69. 69.
    F. Yuan, in CMOS active inductors and transformers: principle, implementation and applications (Springer, 2008)Google Scholar
  70. 70.
    S. Mohan, S. Hershenson, M. Boyd, T. Lee, Simple accurate expressions for planar spiral inductances. IEEE J. Solid-State Circ. 34(10), 1419–1424 (1999)CrossRefGoogle Scholar
  71. 71.
    B. Sun, F. Yuan, A New inductor series-peaking technique for bandwidth enhancement of CMOS current-mode circuits. Analog Integr. Circ. Sig. Process 37, 259–264 (2003)CrossRefGoogle Scholar
  72. 72.
    F. Yuan, in CMOS Current-Mode Circuits for Data Communications (Springer, 2007)Google Scholar
  73. 73.
    H.T. Bui, Dual-path and diode-tracking active inductors for MCML gates, in Canadian Conference on Electrical and Computer Engineering (2006), pp. 1060–1063Google Scholar
  74. 74.
    S.M. Masood, in Active Loads in Current-Mode Logic (CML) Topology (Technical University of Denmark, 2006)Google Scholar
  75. 75.
    A. Tajalli, E. Vittoz, Y. Leblebici, Ultra low power subthreshold MOS current mode logic circuits using a novel load device concept, in Proceedings of International Conference on Solid State Circuits (Munich, 2007), pp. 304–307Google Scholar
  76. 76.
    A. Tajalli, E. VIttoz, Y. Leblebici, E.J. Brauer, Ultra-low power subthreshold current-mode logic utilizing PMOS load device. Electr. Lett. 43(17), 911–912 (2007)CrossRefGoogle Scholar
  77. 77.
    M. Alioto, Y. Leblebici, Analysis and design of ultra-low power subthreshold MCML gates, in Proceedings of IEEE International Symposium on Circuits and System (Taipei, 2009), pp. 2557–2560Google Scholar
  78. 78.
    E.A. Shapiro, E.G. Friedman, Performance characteristics of 14 nm near threshold MCML circuits, in Proceedings of IEEE Unified Conference on SOI-3D-Subthreshold Microelectronics Technology (Monterey, 2013), pp. 1–2Google Scholar
  79. 79.
    A. Tajalli, Y. Leblebici, Subthreshold source-coupled logic, in Advanced Circuits for Emerging Technologies, ed. by K. Iniewski (Wiley, Hoboken, NJ, USA, 2012)Google Scholar
  80. 80.
    A. Tajalli, E.J. Brauer, Y. Leblebici, E. Vittoz, Subthreshold source-coupled logic circuits for ultra-low-power applications. IEEE J. Solid-State Circ. 43(7), 1699–1710 (2008)CrossRefGoogle Scholar
  81. 81.
    R. Cao, J. Hu, Near-threshold computing and minimum supply voltage of single-rail MCML circuits. J. Electr. Comput. Eng. 2014, 10 (2014). (Article ID 836019)Google Scholar
  82. 82.
    F. Cannillo, C. Toumazou, T.S. Lande, Nanopower subthreshold MCML in submicrometer CMOS technology. IEEE Trans. Circ. Syst. I Regul. Papers 56(8), 1598–1611 (2009)MathSciNetCrossRefGoogle Scholar
  83. 83.
    M.H. Anis, M.I. Elmasry, Self-timed MOS current mode logic for digital applications, in Proceedings of IEEE International Symposium on Circuits and Systems (2002), pp. 113–116Google Scholar
  84. 84.
    M.W. Allam, M.I. Elmasry, Dynamic current mode logic (DyMCML): a new low-power high performance logic style. IEEE J. Solid-State Circ. 36(3), 550–558 (2001)CrossRefGoogle Scholar
  85. 85.
    G. Caruso, D. Sclafani, Analysis of compressor architectures in MOS current-mode logic, in Proceedings of IEEE International Conference on Electronics, Circuits, and Systems (Athens, 2010), pp. 13–16Google Scholar
  86. 86.
    J.B. Kim, Low-power MCML circuit with sleep-transistor, in Proceedings of IEEE International Conference on Application-Specific Integrated Circuits (2009), pp. 25–28Google Scholar
  87. 87.
    K. Zou, J. Hu, A power-gating scheme for MOS current mode logic circuits. Telkomnika 11(10), 6111–6119 (2013)Google Scholar
  88. 88.
    Y. Wu, X. Fan, H. Ni, J. Hu, Low-power near-threshold MOS current mode logic with power-gating techniques, in Proceedings of the 2nd International Conference on Computer Science and Electronics Engineering, Changsha (2013), pp. 1694–1697Google Scholar
  89. 89.
    A. Cevrero, F. Regazzoni, M. Schwander, S. Badel, P. Ienne, Y. Leblebici, Power-gated MOS current mode logic (PG-MCML): a power aware DPA-resistant standard cell library, in Proceedings of in IEEE International Conference on Design Automation (New York, 2011), pp. 1014–1019Google Scholar
  90. 90.
    J.K. Shin, T.W. Yoo, M.S. Lee, Design of half-rate linear phase detector using MOS current mode logic gates for 10-Gb/s clock and data recovery circuits, in Proceedings of International Conference on Advanced Communication Technology (Phoenix Park, 2005), pp. 205–210Google Scholar
  91. 91.
    P. Heydari, R. Mohavavelu, Design of ultra high-speed CMOS CML buffers and latches, in Proceedings of IEEE Conference on Circuits and Systems (2003), pp. 208–211Google Scholar
  92. 92.
    M. Sumanthi, Y.C. Kartheek, Performance and analysis of CML logic gates and latches, in Proceedings of IEEE International Symposium on Microwave, Antenna, Propagation and EMC Technologies for Wireless Communications, Hangzhou (2007), pp. 1428–1432Google Scholar
  93. 93.
    P. Heydari, R. Mohavavelu, Design of ultra high-speed CMOS CML buffers and latches, in Proceedings of the International Symposium on Circuits and Systems (2003), pp. II-208–II-211Google Scholar
  94. 94.
    M. Usama, Tad A. Kwasniewski, Design and comparison of CMOS current mode logic latches, in Proceedings of IEEE International Symposium on Circuits and Systems (2004), pp. 353–356Google Scholar
  95. 95.
    M. Alioto, R. Mita, G. Palumbo, Design of high-speed power efficient MOS current mode logic frequency dividers. IEEE Trans. Circ. Syst. II: Expr. Briefs 53(11), 1165–1169 (2006)CrossRefGoogle Scholar
  96. 96.
    R. Nonis, E. Palumbo, P. Palestri, L. Selmi, A design methodology for MOS current-mode logic frequency dividers. IEEE Trans. Circ. Syst. I Regul. Papers 54(2), 245–254 (2007)CrossRefGoogle Scholar
  97. 97.
    B. Razavi, A model to understand current consumption, maximum operating frequency and scaling trends of MCML frequency dividers. RF Microelectronics (Prentice Hall, 1998)Google Scholar
  98. 98.
    U. Singh, M.M. Green, High-frequency CML clock dividers in 0.13-m CMOS operating up to 38 GHz. IEEE J. Solid-State Circ. 40(8), 1658–1661 (2005)CrossRefGoogle Scholar
  99. 99.
    R.K. Agrawal, N. Pandey, K. Gupta, Implementation of PFSCL razor flip flop, in Proceedings of IEEE 2017 International Conference on Computing Methodologies and Communication, ICCMC, pp. 6–11Google Scholar
  100. 100.
    Radhika, N. Pandey, K. Gupta, M. Gupta, Low power D-latch design using MCML tri-state buffers, in Proceedings of IEEE International Conference on Signal Processing and Integrated Networks (SPIN) (2014), pp. 531–534Google Scholar
  101. 101.
    M. Nocente, D. Fontanelli, P. Palestri, R. Nonis, D. Esseni, L. Selmi, A numerical model for the oscillation frequency, the amplitude and the phase-noise of MOS-current-mode-logic ring oscillators. Int. J. Circ. Theory Appl. 38(6), 591–623 (2009)zbMATHGoogle Scholar
  102. 102.
    A.H. Ismail, M. Sharifkhani, M I. Elmasry, On the design of low power MCML based ring oscillators, in Proceedings of IEEE Canadian Conference on Electrical and Computer Engineering (2004), pp. 2383–2386Google Scholar
  103. 103.
    A. Tyagi, N. Pandey, K. Gupta, PFSCL based linear feedback shift register, in Proceedings of IEEE International Conference on Computational Techniques in Information and Communication Technologies, ICCTICT (2016), pp. 580–585Google Scholar
  104. 104.
    S. Agarwal, N. Pandey, K. Gupta, Bharat Choudhary, Design of MCML based LFSR for low power and mixed signal applications, in Proceedings of Annual IEEE India International Conference INDICON (2015), pp. 1–6Google Scholar
  105. 105.
    K. Gupta, N. Pandey, M. Gupta, A new active shunt-peaked MCML based high performance 1:8 demultiplexer for serial communication. Int. J. Eng. Technol. 2(10), 4632–4639 (2010)Google Scholar
  106. 106.
    K. Gupta, U. Mittal, R. Baghla, P. Shukla, N. Pandey, On the implementation of PFSCL serializer, in Proceedings of IEEE International Conference on Signal Processing and Integrated Networks (SPIN) (2016), pp. 436–440Google Scholar
  107. 107.
    K. Gupta, U. Mittal, R. Baghla, N. Pandey, Implementation of PFSCL based demultiplexer, in Proceedings of IEEE International Conference on Computational Techniques in Information and Communication Technologies, ICCTICT (2016), pp. 490–494Google Scholar
  108. 108.
    L. Li, S. Raghavendran, D.T. Comer, CMOS current mode logic gates for high speed applications, in Proceedings of NASA Symposium on VLSI Design (Coeurd’ Alene, Idaho, 2005), pp. 1–3Google Scholar
  109. 109.
    S. Kabiri, M. Shams, Implementation of MCML universal logic for 10 GHz range in a 0.13 µm CMOS technology, in Proceedings of the International Symposium on Circuits and Systems (2004), pp. 653–656Google Scholar
  110. 110.
    P. Heydari, Design and analysis of low-voltage current-mode logic buffers, in Proceedings of IEEE International Symposium on Quality Electronic Design (2003), pp. 293–298Google Scholar
  111. 111.
    M. Alioto, G. Palumbo, Power aware design of nanometer MCML tapered buffers. IEEE Trans. Circ. Syst. II: Expr. Briefs 55(1), 16–20 (2008)Google Scholar
  112. 112.
    Y.M. El-Hariry, A.H. Madian, MOS current mode logic realization of digital arithmetic circuits, in Proceedings of International Conference on Microelectronics (Cairo, 2010), pp. 128–131Google Scholar
  113. 113.
    S. Badel, Y. Leblebici, Tri-state buffer/bus driver circuits in MOS current-mode logic, in Proceedings of Research in Microelectronics and Electronics Conference (Bordeaux, 2007), pp. 237–240Google Scholar
  114. 114.
    N. Haiyan, H. Jianping, The layout implementations of high-speed low-power MCML cells, in Proceedings of IEEE International Conference on Electronics, Communication and Control (Zhejiang, 2011), pp. 2936–2939Google Scholar
  115. 115.
    M. Haghi, J. Draper, A single-event upset hardening technique for high speed MOS current mode logic, in Proceedings of IEEE International Symposium on Circuits and Systems (Paris, 2010), pp. 4137–4140Google Scholar
  116. 116.
    S. Khabiri, M. Shams, An MCML four-bit ripple-carry adder design in 1 GHz range, in Proceedings of IEEE International Symposium on Circuits and Systems (2005), pp. 1634–1637Google Scholar
  117. 117.
    B. Liang, K. Ma, Z. Ding, X. Fu, The structure design of MOS current mode logic adder, in Proceedings of International Conference on Millimeter Wave Technology, vol. 4 (Shenzen, 2012), pp. 1–4Google Scholar
  118. 118.
    Y. Delican, T. Yildirim, High performance 8-bit MUX based multiplier design using MOS current mode logic, in Proceedings of International Conference on Electrical and Electronics Engineering (Bursa, 2011), pp. II-89–II-93Google Scholar
  119. 119.
    A. Saha, D. Pal, M. Chandra, M.K. Goswami, Novel high speed MCML 8-bit by 8-bit multiplier, in Proceedings of International Conference on Devices and Communications (Mesra, 2011), pp. 1–5Google Scholar
  120. 120.
    V. Srinivasan, S.H. Dong, J.B. Sulistyo, Gigahertz-range MCML multiplier architectures, in Proceedings of the International Symposium on Circuits and Systems (2004), pp. 785–788Google Scholar
  121. 121.
    Y. Delcan, A. Morgul, High performance 16-bit MCML multiplier, in Proceedings of IEEE European Conference on Circuit Theory and Design, Antalya (2009), pp. 157–160Google Scholar
  122. 122.
    M. Mizuno, M. Yamashina, K. Furuta, H. Igura, H. Abiko, K. Okabe, A. Ono, H. Yamada, A GHz MOS adaptive pipeline technique using variable delay circuits, in IEEE International Symposium on VLSI circuits (1994), pp. 27–28Google Scholar
  123. 123.
    T.W. Kwan, M. Shams, Multi-GHz energy-efficient asynchronous pipelined circuits in MOS current mode logic, in Proceedings of IEEE International Symposium on Circuits and Systems (2004), pp. II-645–II-648Google Scholar
  124. 124.
    T.W. Kwan, M. Shams, Design of multi-GHz asynchronous pipelined circuits in MOS current mode logic, in Proceedings of International Conference on VLSI Design (2005), pp. 301–305Google Scholar
  125. 125.
    T.W. Kwan, M. Shams, Design of asynchronous circuit primitives using MOS current mode logic, in Proceedings of International Conference on VLSI Design (2004), pp. 170–173Google Scholar
  126. 126.
    T.W. Kwan, M. Shams, Design of high-performance power-aware asynchronous pipelined circuits in MOS current mode logic, in Proceedings of IEEE International Symposium on Asynchronous Circuits and Systems (2005), pp. 1–10Google Scholar
  127. 127.
    K. Gupta, N. Pandey, M. Gupta, Multi-threshold MOS current mode logic based asynchronous pipeline circuits. ISRN Electr 2012, 7 (2012). (Article ID 529194)Google Scholar
  128. 128.
    K. Gupta, N. Pandey, M. Gupta, A novel active shunt-peaked MCML array multiplier. J. Multi Discipl. Eng. Technol. 6(2), 8 (2012)Google Scholar
  129. 129.
    K. Gupta, N. Pandey, N. Saxena, S. Dutta, Implementation and performance comparison of a four-bit ripple-carry adder using different MOS current mode logic topologies, in Proceedings of International Conference on Computational Science and Its Applications—ICCSA (2017), pp. 299–313Google Scholar
  130. 130.
    N. Pandey, K. Gupta, S. Gupta, S. Kumari, MCML based priority encoders, in 4th International Conference on Recent Advances in Engineering Science and Management (ICRAESM-17), pp. 246–254Google Scholar
  131. 131.
    K. Gupta, P. Shukla, N. Pandey, On the implementation of PFSCL adders, in Second International Innovative Applications of Computational Intelligence on Power, Energy and Controls with their Impact on Humanity (2016), pp. 287–291Google Scholar
  132. 132.
    K. Gupta, R. Tanwar, N. Pandey, M. Gupta, A novel high speed MCML square root carry select adder for mixed-signal applications, in Proceedings of IEEE International Conference on Multimedia, Signal Processing and Communication Technologies (2013), pp. 194–197Google Scholar
  133. 133.
    K. Gupta, N. Pandey, M. Gupta, Low power multi-threshold MOS current mode logic asynchronous pipeline circuits, in Proceedings of IEEE 5th India International Conference on Power Electronics (IICPE) (2012), pp. 1–4Google Scholar
  134. 134.
    K. Gupta, N. Pandey, M. Gupta, A novel active shunt-peaked MOS current mode logic C-element for asynchronous pipelines, in Proceedings of IEEE International Conference on Multimedia, Signal Processing and Communication Technologies (2011), pp. 122–125Google Scholar
  135. 135.
    K. Gupta, N. Pandey, M. Gupta, Shunt-peaking in MCML memory element design in 0.18 μm CMOS technology, in Proceedings of Annual IEEE India Conference (INDICON) (2010), pp. 1–4Google Scholar

Copyright information

© Springer Nature Singapore Pte Ltd. 2020

Authors and Affiliations

  • Kirti Gupta
    • 1
  • Neeta Pandey
    • 2
  • Maneesha Gupta
    • 3
  1. 1.Department of Electronics and CommunicationBharati Vidyapeeth’s College of EngineeringNew DelhiIndia
  2. 2.Department of Electronics and CommunicationDelhi Technological UniversityNew DelhiIndia
  3. 3.Department of Electronics and CommunicationNetaji Subhas University of TechnologyDwarkaIndia

Personalised recommendations