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Design a 4-Bit Carry Look-Ahead Adder Using Pass Transistor for Less Power Consumption and Maximization of Speed

  • Burhan Khan
  • Suraj PattanaikEmail author
Conference paper
Part of the Lecture Notes on Data Engineering and Communications Technologies book series (LNDECT, volume 37)

Abstract

A high-speed power-efficient 4-bit carry look-ahead adder (CLA) is designed by using pass transistor logic (PTL). To overcome the issues of delay as well as power consumption, the PTL has been deliberately used in integrated circuits design. The pass transistor logic is a better way to implement circuits for high-speed and low-power applications in less number of transistors. Parameters like delay, power consumption, and energy are reduced so much as compared to available logic styles such as static CMOS logic, DOMINO logic, and sub-threshold regime logic. All the analysis and simulations have been done by Cadence Virtuoso simulation tool in 180 nm technology with the supply voltage of 1.8 V at 5 MHz operating frequency.

Keywords

Carry look-ahead adder PTL Cadence Virtuoso tool Delay Power Energy Computer applications Chip design 

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Copyright information

© Springer Nature Singapore Pte Ltd. 2020

Authors and Affiliations

  1. 1.Electronics and Communication Engineering DepartmentCAPGS, BPUTRourkelaIndia
  2. 2.Electronics and Communication Engineering DepartmentGIETBhubaneswarIndia

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