Symmetric Tree Interconnects Modeling with Elementary Distributed RC-Line

  • Blaise RaveloEmail author


Over the last five decades, the semiconductor technology progress manifests with the growth of analog and digital circuit integration density and also the increase of operating data speed.


  1. 1.
    M.-E. Hwang, S.-O. Jung, K. Roy, Slope interconnect effort: gate-interconnect interdependent delay modeling for early CMOS circuit simulation. IEEE Trans. CAS I 56(7), 1428–1441 (2009)MathSciNetGoogle Scholar
  2. 2.
    M. Ghoneima, Y. Ismail, M.M. Khellah, J. Tschanz, V. De, Serial-link bus: a low-power on-chip bus architecture. IEEE Trans. CAS I 56(9), 2020–2032 (2009)MathSciNetGoogle Scholar
  3. 3.
    B. Yun, S.S. Wong, Optimization of driver preemphasis for on-chip interconnects. IEEE Trans. CAS I 56(9), 2033–2041 (2009)MathSciNetGoogle Scholar
  4. 4.
    J. Cong, L. He, C.K. Koh, P.H. Madden, Performance optimization of VLSI interconnect layout. Integr. VLSI J. 21(1–2), 1–94 (1996)CrossRefGoogle Scholar
  5. 5.
    L. Hungwen, S. Chauchin, L.J. Chien-Nan, A tree-topology multiplexer for multiphase clock system. IEEE Trans. CAS I 56(1), 124–131 (2009)MathSciNetGoogle Scholar
  6. 6.
    N. Rakuljic, I. Galton, Tree-structured DEM DACs with arbitrary numbers of levels. IEEE Trans. CAS I 52(2), 313–322 (2010)MathSciNetGoogle Scholar
  7. 7.
    G.F. Bo, P. Ampadu, On hamming product codes with type-II hybrid ARQ for on-chip interconnects. IEEE Trans. CAS I 56(9), 2042–2054 (2009)MathSciNetGoogle Scholar
  8. 8.
    P.P. Sotiriadis, A.P. Chandrakasan, A bus energy model for deep submicron technology. IEEE Trans. VLSI Syst. 10(3), 341–350 (2002)CrossRefGoogle Scholar
  9. 9.
    J.D. Meindl, Interconnect opportunities for gigascale integration. IEEE Micro. 23(3), 28–35 (2003)CrossRefGoogle Scholar
  10. 10.
    B. Ravelo, Delay modelling of high-speed distributed interconnect for the signal integrity prediction. Eur. Phys. J. Appl. Phys. (EPJAP) 57(31002), 1–8 (2012)Google Scholar
  11. 11.
    V.V. Deodhar, J.A. Davis, Optimal voltage scaling, repeater insertion, and wire sizing for wave-pipelined global interconnects. IEEE Trans. CAS I 55(4), 1023–1030 (2008)MathSciNetGoogle Scholar
  12. 12.
    D. Velenis, R. Sundaresha, E.G. Friedman, Buffer sizing for delay uncertainty induced by process variations, in Proceedings of IEEE International Conference on Electronics, CAS, pp. 415–418, Dec 2004Google Scholar
  13. 13.
    B. Ravelo, A. Perennec, M. Le Roy, Equalization of interconnect propagation delay with negative group delay active circuits, in 11th IEEE Workshop on SPI, Genova, Italy, pp. 15–18, May 2007Google Scholar
  14. 14.
    B. Ravelo, A. Perennec, M. Le Roy, Application of negative group delay active circuits to reduce the 50% propagation delay of RC-line model, in 12th IEEE Workshop on SPI, Avignon, France, May 2008Google Scholar
  15. 15.
    B. Ravelo, A. Perennec, M. Le Roy, Experimental validation of the RC-interconnect effect equalization with negative group delay active circuit in planar hybrid technology, in 13th IEEE Workshop on SPI, Strasbourg, France, May 2009Google Scholar
  16. 16.
    B. Ravelo, A. Perennec, M. Le Roy, New technique of inter-chip interconnect effects equalization with negative group delay active circuits, in VLSI Intech, Chap. 20, ed. by Z.F. Wang (2010), pp. 409–434Google Scholar
  17. 17.
    International Technology Roadmap for Semiconductors Update Overview (2008). [Online]. Available:
  18. 18.
    J.J. Wells, Faster than fiber: the future of multi-Gb/s wireless. IEEE Microwave Mag. 104–112 (2009)CrossRefGoogle Scholar
  19. 19.
    R.M. Henderson, K.J. Herrick, T.M. Weller, S.V. Robertson, R.T. Kihm, L.P.B. Katehi, Three-dimensional high-frequency distribution networks—Part II: packaging and integration. IEEE Trans. MTT 48(10), 1643–1651 (2000)CrossRefGoogle Scholar
  20. 20.
    M. Voutilainen, M. Rouvala, P. Kotiranta, T. Rauner, Multi-gigabit serial link emissions and mobile terminal antenna interference, in 13th IEEE Workshop on SPI, Strasbourg, France, May 2009Google Scholar
  21. 21.
    Agilent EEsof EDA, Overview: Electromagnetic Design System (EMDS) (2008, Sept). [Online]. Available:
  22. 22.
    Ansoft Corporation, Simulation Software: High-Performance Signal and Power Integrity. Internal Report (2006)Google Scholar
  23. 23.
    ANSYS, Unparalleled Advancements in Signal- and Power-Integrity, Electromagnetic Compatibility Testing (2009, June 16). [Online]. Available:
  24. 24.
    North East Systems Associates (NESA), RJ45 Interconnect Signal Integrity (2010 CST AG). [Online]. Available:
  25. 25.
    W.C. Elmore, The transient response of damped linear networks. J. Appl. Phys. 19, 55–63 (1948)CrossRefGoogle Scholar
  26. 26.
    P.K. Chan, M.D.F. Schlag, Bounds on signal delay in RC mesh networks. IEEE Trans. CAD 8, 581–589 (1989)CrossRefGoogle Scholar
  27. 27.
    M.A. Horowitz, Timing models for MOS pass networks, in 1983 Proceedings of IEEE ISCAS, pp. 198–201Google Scholar
  28. 28.
    L. Wyatt, Circuit Analysis, Simulation and Design (Elsiever Science, North-Holland, The Netherlands, 1978)Google Scholar
  29. 29.
    D. Standley, J.L. Wyatt Jr., Improved signal delay bounds for RC tree networks, in VLSI Memo, No. 86–317 (MIT, Cambridge, MAS, USA, May 1986)Google Scholar
  30. 30.
    N.K. Jain, V.C. Prasad, A.B. Bhattacharyyaa, Delay-time sensitivity in linear RC tree. IEEE Trans. CAS 34(4), 443–445 (1987)CrossRefGoogle Scholar
  31. 31.
    L. Vandenberghe, S. Boyd, A. El Gamal, Optimizing dominant time constant in RC circuits. IEEE Trans. CAD 17(2), 110–125 (1998)CrossRefGoogle Scholar
  32. 32.
    C.A. Marinov, A. Rubio, The energy bounds in RC circuits. IEEE Trans. CAS I 46(7), 869–871 (1999)CrossRefGoogle Scholar
  33. 33.
    A.C. Deng, Y.C. Shiau, Generic linear RC delay modeling for digital CMOS circuits. IEEE Trans. CAD 9(4), 367–376 (1990)CrossRefGoogle Scholar
  34. 34.
    R. Gupta, B. Tutuianu, L.T. Pileggi, The Elmore delay as a bound for RC trees with generalized input signals. IEEE Trans. CAD 16(1), 95–104 (1997)CrossRefGoogle Scholar
  35. 35.
    A.B. Kahng, S. Muddu, An analytical delay model of RLC interconnects. IEEE Trans. CAD 16, 1507–1514 (1997)CrossRefGoogle Scholar
  36. 36.
    Y. Ismail, E.G. Friedman, J.L. Neves, Figures of merit to characterize the importance of on-chip inductance, in 1998 Proceedings of the 35th Annual ACM IEEE Design Automation Conference, San Francisco, CA (USA), pp. 560–565Google Scholar
  37. 37.
    Y.I. Ismail, E.G. Friedman, J.L. Neves, Equivalent Elmore delay for RLC trees. IEEE Trans. CAD 19(1), 83–97 (2000)CrossRefGoogle Scholar
  38. 38.
    A. Ligocka, W. Bandurski, Effect of inductance on interconnect propagation delay in VLSI circuits, in Proceedings of 8th Workshop on SPI, pp. 121–124, 9–12 May 2004Google Scholar
  39. 39.
    G. Chen, E.G. Friedman, Transient response of a distributed RLC interconnect based on direct pole extraction. J. Circuits Syst. Comput. 18(7), 1263–1285 (2009)CrossRefGoogle Scholar
  40. 40.
    T. Eudes, B. Ravelo, Analysis of multi-gigabits signal integrity through clock H-tree. Int. J. Circuit Theory Appl. 41(5), 535–549 (2013)CrossRefGoogle Scholar
  41. 41.
    T. Eudes, B. Ravelo, A. Louis, Transient response characterization of the high-speed interconnection RLCG-model for the signal integrity analysis. Prog. Electromagnet. J. (PIER) 112, 183–197 (2011)CrossRefGoogle Scholar
  42. 42.
    T. Eudes, B. Ravelo, A. Louis, Experimental validations of a simple PCB interconnect model for high-rate signal integrity. IEEE Trans. EMC 54(2), 397–404 (2012)Google Scholar
  43. 43.
    B. Ravelo, T. Eudes, Fast estimation of RL-loaded microelectronic interconnections delay for the signal integrity prediction. Int. J. Numer. Model 25(4), 338–346 (2012)CrossRefGoogle Scholar
  44. 44.
    B. Ravelo, A.K. Jastrzebski, Modelling of symmetrical distributed clock RC H-tree, in Proceedings of 2012 International Symposium on Electromagnetic Compatibility (EMC EUROPE), Rome, Italy, pp. 1–6, 17–21 Sept 2012Google Scholar

Copyright information

© Springer Nature Singapore Pte Ltd. 2020

Authors and Affiliations

  1. 1.Graduate Engineering School, ESIGELECSotteville les RouenFrance

Personalised recommendations