Surface Potential Profile of Nano Scaled Work Function Engineered Gate Recessed IR Silicon on Insulator MOSFET

  • Tiya Dey Malakar
  • Moutushi SinghEmail author
  • Subir Kumar Sarkar
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 1065)


In this present analysis, we represent the surface potential profile of horizontally graded binary metal alloy gate (work function engineered gate) recessed source/drain (Re S/D) SOI/SON MOSFET with additional insulator region (I-SOI). The proposed structure is akin to that of the recessed S/D SOI MOSFET with the exception that there is an insulator region of high-k dielectric in between the channel and drain region. The analytical surface potential model has been developed by solving two-dimensional Poisson’s equation in the channel region considering appropriate boundary condition with a parabolic potential profile.


High-k dielectric Short channel effects (SCEs) Recessed source/drain (Re S/D) Work function engineered gate (WFEG) 


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Copyright information

© Springer Nature Singapore Pte Ltd. 2020

Authors and Affiliations

  • Tiya Dey Malakar
    • 1
  • Moutushi Singh
    • 2
    Email author
  • Subir Kumar Sarkar
    • 3
  1. 1.Department of Electronics and Communication EngineeringRCC Institute of Information TechnologyKolkataIndia
  2. 2.Department of Information TechnologyInstitute of Engineering and ManagementKolkataIndia
  3. 3.Department of ETCEJadavpur UniversityKolkataIndia

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