Improved Leakage Current Performance in Domino Logic Using Negative Differential Resistance Keeper

  • Deepika BansalEmail author
  • Bal Chand Nagar
  • Brahamdeo Prasad Singh
  • Ajay Kumar
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 1059)


In this article, a new improved domino logic-based topology is proposed for achieving improved leakage current performance using negative differential resistance (NDR) keeper circuit. The NDR keeper is used to preserve the correct output level and reduced the power consumption with negative resistance. The proposed domino circuit is verified using Synopsys HSPICE simulator with 45 nm and 16 nm technology parameter provided by PTM model library. The simulation outcomes validate the improved performance of the proposed circuit in terms of leakage power consumption and power delay product. Simulation results show that the proposed NDR keeper circuit provides lower static and dynamic power consumption up to 26 and 30% respectively for 16nm technology, as compared to the domino circuits.


Domino logic Negative differential resistance Leakage current Power consumption MOSFET 


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Copyright information

© Springer Nature Singapore Pte Ltd. 2020

Authors and Affiliations

  • Deepika Bansal
    • 1
    Email author
  • Bal Chand Nagar
    • 1
    • 2
  • Brahamdeo Prasad Singh
    • 1
  • Ajay Kumar
    • 1
  1. 1.Manipal University JaipurJaipurIndia
  2. 2.National Institute of Technology PatnaPatnaIndia

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