Detection and Analysis of Congestion of Nodes in Many-Core Processor

  • Nishin Jude C. AbrahamEmail author
  • D. Radha
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 1045)


The recent trend in developing embedded systems tends towards the many-core processors. The essence of the many-core can be experienced only when the communication and the allocation of the packets to different cores are considered and optimised. The increase in the number of cores within a semiconductor chip increases the complexity of the communication between the cores. The cores need to communicate to share the data in their cache instead of accessing the data from main memory. The major hindrance in the development of an effective communication system for inter-core communication is the phenomenon of congestion. The proposed work is to detect the congestion before a router causes further bottleneck for communication, rather than managing the congestion. The delay incurred by a router for processing a flit can be found by counting the number of clock cycles elapsed during the flits lifecycle on that router. A threshold on the delay may imply the upcoming congestion on the router. This delay can be useful for finding the idleness and activeness of routers. Identifying the router congestion in a many-core processor can later be useful for effective routing by managing the congestion. These results can be extended further for analysing the effects of congestion on various applications and also for developing routing techniques that can improve the multicore performance. The work uses Booksim2 simulator to analyse the system characteristics.


Congestion Delay Many-core processors Packet injection Routing 


  1. 1.
    Teja, S.T., Narayana, T.V.V.S., Vinodhini, M., Murty, N.S.: Joint crosstalk avoidance with multiple bit error correction coding technique for NoC interconnect. In: 7th IEEE International conference on Advances in Computing, Communications and Informatics (ICACCI), PES Institute of Technology, Bengaluru, South campus, India (2018)Google Scholar
  2. 2.
    Daneshtalab, M., Sobhani, A., Afzali-Kusha, A., Fatemi, O., NavabiM, Z.: NoC Hot spot minimization using AntNet dynamic routing algorithm. In: IEEE 17th International Conference on Application-Specific Systems, Architectures and Processors (ASAP’06), 11–13 Sept. 2006Google Scholar
  3. 3.
    Raj, R.S.R., Das, A., Jos, J.: Implementation and analysis of hotspot mitigation in mesh NoC’s by cost-effective deflection routing technique. In: 2017 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 23–25 Oct. 2017Google Scholar
  4. 4.
    Moscibroda, T., Mutlu, O.: A case for bufferless routing in on-chip networks. In: Proceedings of the 36th Annual International Symposium on Computer Architecture, 20–24 June 2009Google Scholar
  5. 5.
    Kuo, Y.-H., Tsai, P.-A., Ho, H.-P., Chang, E.-J., Hsin, H.-K., Wu, A.-Y.: Path diversity-aware adaptive routing in network-on-chip systems. In: 2012 IEEE 6th International Symposium on Embedded Multicore SoC, 20–22 Sept. 2012Google Scholar
  6. 6.
    Debinath, M., Konstantinou, D.: Low cost congestion management in networks-on-chip using edge and in-network traffic throttling. In: Proceedings of the 2nd International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems, 20–25 Jan. 2017Google Scholar
  7. 7.
    Avani, P., Agrawal, S.: Efficient dynamic virtual channel architecture for NoC. In: Symposium on VLSI Design and Embedded Computing (VDEC’18), co-affiliated with Seventh International Conference on Advances in Computing, Communications and Informatics (ICACCI-2018), PES Institute of Technology, Bengaluru, South Campus, India, 2018 Google Scholar
  8. 8.
    Blagodurov, S Zhuravlev, & Fedorova, A.: Contention-aware scheduling on multicore systems. ACM Trans. Comput. Syst. 28(4) 4 Dec. 2010Google Scholar
  9. 9.
    Jiang, N., Becker, D.U., Michelogiannakis, G., Balfour, J., Towles, B., Shaw, D.E., Kim, J., Dally, W.J.: A detailed and flexible cycle-accurate network-on-Chip simulator. In: IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), 15 Jul. 2013Google Scholar

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© Springer Nature Singapore Pte Ltd. 2020

Authors and Affiliations

  1. 1.Department of Computer Science & EngineeringAmrita School of Engineering, Amrita Vishwa VidyapeethamBengaluruIndia

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