Implementation of Asynchronous Cache Memory

  • Jigjidsuren BattogtokhEmail author
Conference paper
Part of the Smart Innovation, Systems and Technologies book series (SIST, volume 156)


This paper presents a novel asynchronous instruction cache suitable for self-timed system. The DCVSL is useful to make a completion signal which is a reference for handshake control. The proposed CAM is a very simple extension of the basic circuitry that makes a completion signal based on DI model. The cache has 2.75 KB CAM for 8 KB instruction memory. We designed and simulated the proposed asynchronous cache including content addressable memory.




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© Springer Nature Singapore Pte Ltd. 2020

Authors and Affiliations

  1. 1.Department of Electronics and Communication EngineeringSchool of Engineering and Applied Sciences, National University of MongoliaUlaanbaatarMongolia

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