Performance Analysis of Computational Neuroscience Software NEURON on Knights Corner Many Core Processors

  • Pramod S. Kumbhar
  • Subhashini Sivagnanam
  • Kenneth Yoshimoto
  • Michael Hines
  • Ted Carnevale
  • Amit MajumdarEmail author
Conference paper
Part of the Communications in Computer and Information Science book series (CCIS, volume 964)


In this paper we analyze the performance of the computational neuroscience tool NEURON on Intel Knights Corner processors. Knights Corner was the many core processor that was followed by Knights Landing processors. NEURON is a widely used simulation environment for modeling individual neurons and network of neurons. NEURON is used to simulate large models requiring high performance computing, and understanding performance of NEURON on many core processors is of interest to the neuroscience community, as well as to the high performance computing community. NEURON supports parallelization using Message Passing Interface (MPI) library. Parallel performance of NEURON has been analyzed on various types of high performance resources. We analyze the performance and load balance of NEURON for two different size problems on Knights Corner. We use the TAU and Vampir tool to analyze load imbalance issues of these runs. We compare performance on the host SandyBridge processors of Knights Corner versus on the Many Integrated Core (MIC) cores of Knights Corner.


Knights Corner NEURON Load balance 



Authors would like to thank Intel IPCC grant and the European Human Brain Project for providing partial funding for this work.


  1. 1.
    Carnevale, T., Hines, M.: The NEURON Book. Cambridge University Press, Cambridge (2006)CrossRefGoogle Scholar
  2. 2.
  3. 3.
  4. 4.
  5. 5.
    Ippen, T., Eppler, J.M., Plesser, H.E., Diesmann, M.: Constructing neuronal network models in massively parallel environments. Front. Neuroinform. 11 (2017).
  6. 6.
    Hines, M., Kumar, S., Schurmann, F.: Comparison of neuronal spike exchange methods on Blue Gene/P supercomputer. Front. Comput. Neurosci. 5, 49 (2011)CrossRefGoogle Scholar
  7. 7.
    Ananthanarayanan, R., Esser, S.K., Simon, H.D., Modha, D.S.: The cat is out of the bag: cortical simulations with 109 neurons and 1013 synapses. In: Supercomputing 09: Proceedings of the ACM/IEEE SC 2009 Conference on High Performance Networking and Computing, Portland, OR (2009).
  8. 8.
  9. 9.
  10. 10.
  11. 11.
  12. 12.

Copyright information

© Springer Nature Singapore Pte Ltd. 2019

Authors and Affiliations

  • Pramod S. Kumbhar
    • 2
  • Subhashini Sivagnanam
    • 1
  • Kenneth Yoshimoto
    • 1
  • Michael Hines
    • 3
  • Ted Carnevale
    • 3
  • Amit Majumdar
    • 1
    Email author
  1. 1.San Diego Supercomputer CenterUniversity of California San DiegoSan DiegoUSA
  2. 2.Ecole Polytechnique Fédérale de LausanneLaussanneSwitzerland
  3. 3.Neuroscience DepartmentYale UniversityNew HavenUSA

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