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Heterogeneous Integration of Chip-to-Chip Stacks

  • John H. LauEmail author
Chapter

Abstract

As pointed out by Intel (Polka et al. in Intel Technol J 11:197–206 (2007), [1]) sometimes ago that the holy grail to address the memory bandwidth challenge for tera-scale computing is to have 3D chip-to-chip and face-to-face stacked MCP (multi-chip packaging), Fig. 9.1. The top chip is a memory and the bottom chip is a logic or CPU (central processing unit). In this chapter, two examples of heterogeneous integration of chip-to-chip and face-to-face are presented. One is with TSVs in the bottom chip to let go the signals, powers, and grounds and the other is without TSVs but with solder bumps on the larger chip.

References

  1. 1.
    Polka, L. A., H. Kalyanam, G. Hu, and S. Krishnamoorthy, “Package Technology to Address the Memory Bandwidth Challenge for Tera-scale Computing”, Intel Technology Journal, Vol. 11, No. 3, 2007, pp. 197–206.Google Scholar
  2. 2.
    Yu, A. B., A. Kumar, S. W. Ho, W. Y. Hnin, J. H. Lau, C. H. Khong, P. S. Lim, X. W. Zhang, D. Q. Yu, N. Su, B. R. Chew, M. C. Jong, T. C. Tan, V. Kripesh, C. Lee, J. P. Huang, J. Chiang, S. Chen, C.-H. Chiu, C.-Y. Chan, C.-H. Chang, C.-M. Huang, and C.-H. Hsiao, “Development of fine pitch solder microbumps for 3-D chip stacking”, Proceedings of 10th Electronics Packaging Technology Conference, Singapore, December 2008, pp. 387–392.Google Scholar
  3. 3.
    Yu, D. Q., H. Oppermann, J. Kleff, and M. Hutter, “Stability of AuSn eutectic solder cap on Au socket during reflow”, Journal of Materials Science: Materials in Electronics, vol. 20, No. 1, pp. 55–59, 2009.Google Scholar
  4. 4.
    Douglas, M. A., “Trench etch process for a single wafer RIE dry etch reactor”. U.S. Patent 4 855 017 and 4 784 720 and F. Laermer and A. Schilp, “Method of anisotropically etching silicon”. U. S. Patent 5 501 893.Google Scholar
  5. 5.
    Charbonnier, J., S. Cheramy, D. Henry, A. Astier, J. Brun, N. Sillon, A. Jouve, S. Fowler, M. Privet, R. Puligadda, J. Burggraf, and S. Pargfrieder, “Integration of a temporary carrier in a TSV process flow”, Proceedings of 59th Electronic Components and Technology Conference, San Diego, CA, May 2009, pp. 865–871.Google Scholar
  6. 6.
    Premachandran, C. S., N. Rangnathan, S. Mohanraj, C. S. Choong, and K. I. Mahadevan, “A vertical wafer level packaging using through hole filled via interconnects by lift off polymer method for MEMS and 3-D stacking applications”, Proceedings of 55th Electronic Components and Technology Conference, Lake Buena Vista, FL, May–Jun. 2005, pp. 1094–1099.Google Scholar
  7. 7.
    Pang, X., F., T. T. Chua, H. Y. Li, E. B. Liao, W. S. Lee, and F. X. Che, “Characterization and management of wafer stress for various pattern densities in 3-D integration technology,” Proceedings of 60th Electronic Components Technology Conference, Las Vegas, NV, June 2010, pp. 1866–1869.Google Scholar
  8. 8.
    Ayon, A. A., R. Bratt, C. C. Lin, H. H. Sawin, and M. A. Schmidt, “Characterization of a time multiplexed inductively coupled plasma etcher”, Journal of the Electrochemical Society, Vol. 146, No. 1, 1999, pp. 339–349.Google Scholar
  9. 9.
    Chen, K., A. A. Ayon, X. Zhang, and S. M. Spearing, “Effect of process parameters on the surface morphology and mechanical performance of silicon structures after deep reactive ion etching (DRIE)”, Journal of Microelectromechanical Systems, Vol. 11, No. 3, June 2002, pp. 264–275.Google Scholar
  10. 10.
    Iwasaki, T., M. Watanabe, S. Baba, M. Kimura, Y. Hatanaka, S. Idaka, and Y. Yokoyama, “Development of 30 micron pitch bump interconnections for COC-FCBGA”, Proceedings of 56th Electronic Components Technology Conference, San Diego, CA, 2006, pp. 1216–1222.Google Scholar
  11. 11.
    Khong, C., A. Yu, A. Kumar, X. Zhang, V. Kripesh, T. T. Chun, J. H. Lau, and D.-L. Kwong, “Sub-modeling technique for thermomechanical simulation of solder microbumps assembly in 3-D chip stacking”, Proceedings of 11th Electronics Packaging Technology Conference, Singapore, December 2009, pp. 591–595.Google Scholar
  12. 12.
    Yu, A. B., J. H. Lau, S. Ho, A. Kumar, W. Hnin, W. Lee, M. Jong, et al., “Fabrication of High Aspect Ratio TSV and Assembly with Fine-Pitch Low-Cost Solder Microbump for Si Interposer Technology with High-Density Interconnects”, IEEE Transactions on CPMT, Vol. 1, No. 9, September 2011, pp. 1336–1344.Google Scholar
  13. 13.
    Lim, S., V. Rao, H. Yin, W. Ching, V. Kripesh, C. Lee, J. H. Lau, J. Milla, and A. Fenner, “Process Development and Reliability of Microbumps”, IEEE/ECTC Proceedings, December 2008, pp. 367–372. Also, IEEE Transactions on Components and Packaging Technology, Vol. 33, No. 4, 2010, pp. 747–753.Google Scholar
  14. 14.
    Vempati, S., S. Nandar, C. Khong, Y. Lim, V. Kripesh, J. H. Lau, B. P. Liew, K. Y. Au, S. Tamary, A. Fenner, R. Erich, and J. Milla, “Development of 3D Silicon Die Stacked Package Using Flip-Chip Technology with Micro Bump Interconnects”, IEEE/ECTC Proceedings, San Diego, CA, 2009, pp. 980–987.Google Scholar

Copyright information

© Springer Nature Singapore Pte Ltd. 2019

Authors and Affiliations

  1. 1.ASM Pacific TechnologyHong KongHong Kong

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