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Heterogeneous Integration of Memory Stacks

  • John H. LauEmail author
Chapter

Abstract

The first paper on stacking of memory chips in 3D by die-attach material and wire bonding was published by nCHIP (Tuckerman et al. in Laminated memory: a new three-dimensional packaging technology for mcms. IEEE Multi-Chip Module Conference, Santa Cruz, CA, pp 58–63, 1994 [1]) 25 years ago, Fig. 8.1. Since then, memory chips (especially the NAND Flash) stacking by wire bonding have been in high volume production for, e.g., the smartphones, tablets, and solid state drives as shown in Figs. 8.2 and 8.3 by Samsung. It can be seen that 16 48-layer V-NAND 3D flash memory chips are stacked by wirebonding technology. The thickness of each chip is only 40 µm. These are the homogeneous integration of memory stacks.

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© Springer Nature Singapore Pte Ltd. 2019

Authors and Affiliations

  1. 1.ASM Pacific TechnologyHong KongHong Kong

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