Advertisement

Fan-Out Wafer/Panel-Level Packaging for Heterogeneous Integrations

  • John H. LauEmail author
Chapter

Abstract

The first fan-out wafer-level packaging (FOWLP) U.S. patent was filed by Infineon on October 31, 2001.

References

  1. 1.
    Hedler, H., T. Meyer, and B. Vasquez, “Transfer Wafer-Level Packaging”, US Patent 6,727,576, Filed on October 31, 2001, Patented on April 27, 2004.Google Scholar
  2. 2.
    Lau, J.H. 2015. Patent Issues of Fan-Out Wafer/Panel-Level Packaging. Chip Scale Review 19: 42–46.Google Scholar
  3. 3.
    Brunnbauer, M., E. Furgut, G. Beer, T. Meyer, H. Hedler, J. Belonio, E. Nomura, K. Kiuchi, and K. Kobayashi, “An Embedded Device Technology Based on a Molded Reconfigured Wafer”, IEEE/ECTC Proceedings, May 2006, pp. 547–551.Google Scholar
  4. 4.
    Brunnbauer, M., E. Furgut, G. Beer, and T. Meyer, “Embedded Wafer Level Ball Grid Array (eWLB)”, IEEE/EPTC Proceedings, December 2006, pp. 1–5.Google Scholar
  5. 5.
    Eichelberger, C., and R. Wojnarowski, “High-density interconnect with high volumetric efficiency”, US Patent 5,019,946, Filed on September 27, 1988, Patented on May 28, 1991.Google Scholar
  6. 6.
    Fillion, R., R. Wojnarowski, M. Gdula, H. Cole, E. Wildi, and W. Daum, “Method for fabricating an integrated circuit module”, US Patent 5,353,498, Filed on July 9, 1993, Patented on October 11, 1994.Google Scholar
  7. 7.
    Eichelberger, C., “Single-chip modules, repairable multi-chip modules, and methods of fabrication thereof”, US Patent 5,841,193, Filed on May 20, 1996, Patented on November 24, 1998.Google Scholar
  8. 8.
    Lau, J. H., “Patent Issues of Embedded Fan-Out Wafer/Panel Level Packaging”, Proceedings of CSTIC, March 2016, pp. 1–7.Google Scholar
  9. 9.
    Lau, J. H., Reliability of RoHS compliant 2D & 3D IC Interconnects, McGraw-Hill, New York, 2011.Google Scholar
  10. 10.
    Lau, J. H., Through-Silicon Via (TSV) for 3D Integration, McGraw-Hill, New York, 2013.Google Scholar
  11. 11.
    Lau, J. H., 3D IC Integration and Packaging, McGraw-Hill Book Company, NY, 2015.Google Scholar
  12. 12.
    Keser, B., C. Amrine, T. Duong, O. Fay, S. Hayes, G. Leal, W. Lytle, D. Mitchell, and R. Wenzel, “The Redistributed Chip Package: A Breakthrough for Advanced Packaging”, Proceedings of IEEE/ECTC, 2007, pp. 286–291.Google Scholar
  13. 13.
    Kripesh, V., V. Rao, A. Kumar, G. Sharma, K. Houe, X. Zhang, K. Mong, N. Khan, and J. H. Lau, “Design and Development of a Multi-Die Embedded Micro Wafer Level Package”, IEEE/ECTC Proceedings, 2008, pp. 1544–1549.Google Scholar
  14. 14.
    Khong, C., A. Kumar, X. Zhang, S. Gaurav, S. Vempati, V. Kripesh, J. H. Lau, and D. Kwong, “A Novel Method to Predict Die Shift During Compression Molding in Embedded Wafer Level Package”, IEEE/ECTC Proceedings, 2009, pp. 535–541.Google Scholar
  15. 15.
    Sharma, G., S. Vempati, A. Kumar, N. Su, Y. Lim, K. Houe, S. Lim, V. Sekhar, R. Rajoo, V. Kripesh, and J. H. Lau, “Embedded Wafer Level Packages with Laterally Placed and Vertically Stacked Thin Dies”, IEEE/ECTC Proceedings, 2009, pp. 1537–1543. Also, IEEE Transactions on CPMT, Vol. 1, No. 5, May 2011, pp. 52–59.Google Scholar
  16. 16.
    Kumar, A., D. Xia, V. Sekhar, S. Lim, C. Keng, S. Gaurav, S. Vempati, V. Kripesh, J. H. Lau, and D. Kwong, “Wafer Level Embedding Technology for 3D Wafer Level Embedded Package”, IEEE/ECTC Proceedings, 2009, pp. 1289–1296.Google Scholar
  17. 17.
    Lim, Y., S. Vempati, N. Su, X. Xiao, J. Zhou, A. Kumar, P. Thaw, S. Gaurav, T. Lim, S. Liu, V. Kripesh, and J. H. Lau, “Demonstration of High Quality and Low Loss Millimeter Wave Passives on Embedded Wafer Level Packaging Platform (EMWLP)”, IEEE/ECTC Proceedings, 2009, pp. 508–515. Also, IEEE Transactions on Advanced Packaging, Vol. 33, 2010, pp. 1061–1071.Google Scholar
  18. 18.
    Lau, J. H., N. Fan, and M. Li, “Design, Material, Process, and Equipment of Embedded Fan-Out Wafer/Panel-Level Packaging”, Chip Scale Review, Vol. 20, 2016, pp. 38–44.Google Scholar
  19. 19.
    Kurita, Y., T. Kimura, K. Shibuya, H. Kobayashi, F. Kawashiro, N. Motohashi, et al., “Fan-out wafer-level packaging with highly flexible design capabilities”, IEEE/ECTC Proceedings, 2010, pp. 1–6.Google Scholar
  20. 20.
    Motohashi, N., T. Kimura, K. Mineo, Y. Yamada, T. Nishiyama, K. Shibuya, et al., “System in wafer-level package technology with RDL-first process”, IEEE/ECTC Proceedings, 2011, pp. 59–64.Google Scholar
  21. 21.
    Kurita, Y., K. Soejima, K. Kikuchi, M. Takahashi, M. Tago, M. Koike, et al., “A novel “SMAFTI” package for inter-chip wide-band data transfer”, IEEE/ECTC Proceedings, 2006, pp. 289–297.Google Scholar
  22. 22.
    Kawano, M., S. Uchiyama, Y. Egawa, N. Takahashi, Y. Kurita, K. Soejima, et al., “A 3D packaging technology for 4 Gbit stacked DRAM with 3 Gbps data transfer”, Proceedings of IEMT, 2006, pp. 581–584.Google Scholar
  23. 23.
    Kurita, Y., S. Matsui, N. Takahashi, K. Soejima, M. Komuro, M. Itou, et al., “A 3D stacked memory integrated on a logic device using SMAFTI technology”, IEEE/ECTC Proceedings, 2007, pp. 821–829.Google Scholar
  24. 24.
    Kawano, M., N. Takahashi, Y. Kurita, K. Soejima, M. Komuro, S. Matsui, “A 3-D Packaging Technology for Stacked DRAM with 3 Gb/s Data Transfer,” IEEE Transaction on Electron Devices, 2008, pp. 1614–1620.Google Scholar
  25. 25.
    Motohashi, N., Y. Kurita, K. Soejima, Y. Tsuchiya, M. Kawano, “SMAFTI Package with Planarized Multilayer Interconnects”, IEEE/ECTC Proceedings, 2009, pp. 599–606.Google Scholar
  26. 26.
    Kurita, M., S. Matsui, N. Takahashi, K. Soejima, M. Komuro, M. Itou, et al., “Vertical Integration of Stacked DRAM and High-Speed Logic Device Using SMAFTI Technology,” IEEE Transaction on Advanced Packaging, 2009, pp. 657–665.Google Scholar
  27. 27.
    Kurita, Y., N. Motohashi, S. Matsui, K. Soejima, S. Amakawa, K. Masu, et al., “SMAFTI Packaging Technology for New Interconnect Hierarchy,” Proceedings of IITC, 2009, pp. 220–222.Google Scholar
  28. 28.
    Yoon, S., J. Caparas, Y. Lin, and P. Marimuthu, “Advanced Low Profile PoP Solution with Embedded Wafer Level PoP (eWLB-PoP) Technology”, IEEE/ECTC Proceedings, 2012, pp. 1250–1254.Google Scholar
  29. 29.
    Yu, D., “Wafer-Level System Integration (WLSI) Technologies for 2D and 3D System-in-Package”, SEMIEUROPE 2014.Google Scholar
  30. 30.
    Lin, J., J. Hung, N. Liu, Y. Mao, W. Shih, and T. Tung, “Packaged Semiconductor Device with a Molding Compound and a Method of Forming the Same”, US Patent 9,000,584, Filed on December 28, 2011, Patented on April 7, 2015.Google Scholar
  31. 31.
    Tseng, C., Liu, C., Wu, C., and D. Yu, “InFO (Wafer Level Integrated Fan-Out) Technology”, IEEE/ECTC Proceedings, 2016, pp. 1–6.Google Scholar
  32. 32.
    Hsieh, C., Wu, C., and D. Yu, “Analysis and Comparison of Thermal Performance of Advanced Packaging Technologies for State-of-the-Art Mobile Applications”, IEEE/ECTC Proceedings, 2016, pp. 1430–1438.Google Scholar
  33. 33.
    Lau, J. H., “TSV-Less Interposers”, Chip Scale Review, Vol. 20, September/October 2016, pp. 28–35.Google Scholar
  34. 34.
    Yoon, S., P. Tang, R. Emigh, Y. Lin, P. Marimuthu, and R. Pendse, “Fanout Flipchip eWLB (Embedded Wafer Level Ball Grid Array) Technology as 2.5D Packaging Solutions”, IEEE/ECTC Proceedings, 2013, pp. 1855–1860.Google Scholar
  35. 35.
    Lin, Y., W. Lai, C. Kao, J. Lou, P. Yang, C. Wang, and C. Hseih, “Wafer Warpage Experiments and Simulation for Fan-out Chip on Substrate”, IEEE/ECTC Proceedings, 2016, pp. 13–18.Google Scholar
  36. 36.
    Chen, N., T. Hsieh, J. Jinn, P. Chang, F. Huang, J. Xiao, A. Chou, and B. Lin, “A Novel System in Package with Fan-out WLP for high speed SERDES application”, IEEE/ECTC Proceedings, 2016, pp. 1495–1501.Google Scholar
  37. 37.
    Hayashi, N., T. Takahashi, N. Shintani, T. Kondo, H. Marutani, Y. Takehara, K. Higaki, O. Yamagata, Y. Yamaji, Y., Katsumata, and Y. Hiruta, “A Novel Wafer Level Fan-out Package (WFOPTM) Applicable to 50 µm Pad Pitch Interconnects”, IEEE/EPTC Proceeding, December 2011, pp. 730–733.Google Scholar
  38. 38.
    Hayashi, N., H. Machida, N. Shintani, N. Masuda, K. Hashimoto, A. Furuno, K. Yoshimitsu, Y. Kikuchi, M. Ooida, A. Katsumata and Y. Hiruta, “A New Embedded Structure Package for Next Generation, WFOPTM (Wide Strip Fan-Out Package)”. Pan Pacific Symposium Conference Proceedings, February 2014, pp. 1–7.Google Scholar
  39. 39.
    Hayashi, N., M. Nakashima, H. Demachi, S. Nakamura, T. Chikai, Y. Imaizumi, Y. Ikemoto, F. Taniguchi, M. Ooida, and A. Yoshida, “Advanced Embedded Packaging for Power Devices”, IEEE/ECTC Proceedings, 2017, pp. 696–703.Google Scholar
  40. 40.
    Braun, T., K.-F. Becker, S. Voges, T. Thomas, R. Kahle, J. Bauer, R. Aschenbrenner, and K.-D. Lang, “From Wafer Level to Panel Level Mold Embedding”, IEEE/ECTC Proceedings, 2013, pp. 1235–1242.Google Scholar
  41. 41.
    Braun, T., K.-F. Becker, S. Voges, J. Bauer, R. Kahle, V. Bader, T. Thomas, R. Aschenbrenner, and K.-D. Lang, “24”×18” Fan-out Panel Level Packing”, IEEE/ECTC Proceedings, 2014, pp. 940–946.Google Scholar
  42. 42.
    Braun, T., S. Raatz, S. Voges, R. Kahle, V. Bader, J. Bauer, K. Becker, T. Thomas, R. Aschenbrenner, and K. Lang, “Large Area Compression Molding for Fan-out Panel Level Packing”, IEEE/ECTC Proceedings, 2015, pp. 1077–1083.Google Scholar
  43. 43.
    Chang, H., D. Chang, K. Liu, H. Hsu, R. Tai, H. Hunag, Y. Lai, C. Lu, C. Lin, and S. Chu, “Development and Characterization of New Generation Panel Fan-Out (PFO) Packaging Technology”, IEEE/ECTC Proceedings, 2014, pp. 947–951.Google Scholar
  44. 44.
    Liu, H., Y. Liu, J. Ji, J. Liao, A. Chen, Y. Chen, N. Kao, and Y. Lai, “Warpage Characterization of Panel Fab-out (P-FO) Package”, IEEE/ECTC Proceedings, 2014, pp. 1750–1754.Google Scholar
  45. 45.
    Lau, J. H., M. Li, M. Li, T. Chen, I. Xu, X. Qing, Z. Cheng, et al., “Fan-Out Wafer-Level Packaging for Heterogeneous Integration”, Proceedings of IEEE/ECTC, May 2018, pp. 2354–2360.Google Scholar
  46. 46.
    Lau, J. H., M. Li, M. Li, T. Chen, I. Xu, X. Qing, Z. Cheng, N. Fan, E. Kuah, Z. Li, K. Tan, Y. Cheung, E. Ng, P. Lo, K. Wu, J. Hao, S. Koh, R. Jiang, X. Cao, R. Beica, S. Lim, N. Lee, C. Ko, H. Yang, Y. Chen, M. Tao, J. Lo, and R. Lee, “Fan-Out Wafer-Level Packaging for Heterogeneous Integration”, IEEE Transactions on CPMT, 2018, September 2018, pp. 1544–1560.Google Scholar
  47. 47.
    Lau, J. H., M. Li, Y. Lei, M. Li, I. Xu, T. Chen, Q. Yong, Z. Cheng, et al., Reliability of Fan-Out Wafer-Level Heterogeneous Integration”, IMAPS Transactions, Journal of Microelectronics and Electronic Packaging, Vol. 15, Issue 4, October 2018, pp. 148–162.Google Scholar
  48. 48.
    Ko, CT, H. Yang, J. H. Lau, M. Li, M. Li, C. Lin, et al., “Chip-First Fan-Out Panel-Level Packaging for Heterogeneous Integration”, IEEE/ECTC Proceedings, May 2018, pp. 355–363.Google Scholar
  49. 49.
    Ko, CT, H. Yang, J. H. Lau, M. Li, M. Li, C. Lin, J. W. Lin, T. Chen, I. Xu, C. Chang, J. Pan, H. Wu, Q. Yong, N. Fan, E. Kuah, Z. Li, K. Tan, Y. Cheung, E. Ng, K. Wu, J. Hao, R. Beica, M. Lin, Y. Chen, Z. Cheng, S. Koh, R. Jiang, X. Cao, S. Lim, N. Lee, M. Tao, J. Lo, and R. Lee, “Chip-First Fan-Out Panel-Level Packaging for Heterogeneous Integration”, IEEE Transactions on CPMT, September 2018, pp. 1561–1572.Google Scholar
  50. 50.
    Ko, C., H. Yang, J. H. Lau, M. Li, M. Li, et al., “Design, Materials, Process, and Fabrication of Fan-Out Panel-Level Heterogeneous Integration”, IMAPS Transactions, Journal of Microelectronics and Electronic Packaging, Vol. 15, Issue 4, October 2018, pp. 141–147.Google Scholar
  51. 51.
    Hsieh, C., C. Tsai, H. Lee, T. Lee, H. Chang, “Fan-out Technologies for WiFi SiP Module Packaging and Electrical Performance Simulation”, IEEE/ECTC Proceedings, May 2015, pp. 1664–1669.Google Scholar
  52. 52.
    Lin, Y., C. Kang, L. Chua, W. Choi, and S. Yoon, “Advanced 3D eWLB-PoP (embedded Wafer Level Ball Grid Array - Package on Package) Technology”, IEEE/ECTC Proceedings, May 2016, pp. 1772–1777.Google Scholar
  53. 53.
    Lau, J. H., “Fan-Out Wafer-Level Packaging for 3D IC Heterogeneous Integration”, Proceedings of CSTIC, March 2018, pp. VII_1–6.Google Scholar
  54. 54.
    Lau, J. H., “Heterogeneous Integration with Fan-Out Wafer-Level Packaging”, Proceedings of IWLPC, October 2017, pp. 1–25.Google Scholar
  55. 55.
    Lau, J. H., “3D IC Heterogeneous Integration by FOWLP”, Chip Scale Review, Vol. 22, January/February 2018, pp. 16–21.Google Scholar
  56. 56.
    Lim, J., and V. Pandey, “Innovative Integration Solutions for SiP Packages Using Fan-Out Wafer Level eWLB Technology”, IMAPS Proceedings, October 2017, pp. 263–269.Google Scholar
  57. 57.
    Kyozuka, M., T. Kiso, H. Toyazaki, K. Tanaka, and T. Koyama, Development of Thinner POP base Package by Die Embedded and RDL Structure”, IMAPS Proceedings, October 2017, pp. 715–720.Google Scholar
  58. 58.
    Cardoso, A., M. Pires, and R. Pinto, “Thermally Enhanced FOWLP Development of a Power-eWLB Demonstrator”, IEEE/ECTC Proceedings, May 2015, pp. 1682–1688.Google Scholar
  59. 59.
    Cardoso, A., M. Pires, R. Pinto, E. Fernades, I. Barros, H. Kuisma, and S. Nurmi, “Implementation of Keep-Out-Zones to Protect Sensitive Sensor Areas During Backend Processing in Wafer Level Packaging Technology”, IEEE/ECTC Proceedings, May 2016, pp. 1160–1166.Google Scholar
  60. 60.
    Cardoso, A., L. Dias, E. Fernandes, A. Martins, A. Janeiro, P. Cardoso, and H. Barros, “Development of Novel High Density System Integration Solutions in FOWLP—Complex and Thin Wafer-Level SiP and Wafer-Level 3D Packages”, IEEE/ECTC Proceedings, May 2017, pp. 14–21.Google Scholar
  61. 61.
    Seler, E., M. Wojnowski, W. Hartner, J. Böck, R. Lachner, R. Weigel, A. Hagelauer, “3D Rectangular Waveguide Integrated in embedded Wafer Level Ball Grid Array (eWLB) Package”, IEEE/ECTC Proceedings, May 2014, pp. 956–962.Google Scholar
  62. 62.
    Rodrigo, A., B. Isabel, C. José, C. Paulo, C. José, H. Vítor, O. Eoin, and P. Nelson, “Enabling of Fan-Out WLP for More Demanding Applications by Introduction of Enhanced Dielectric Material for Higher Reliability”, IEEE/ECTC Proceedings, May 2014, pp. 935–939.Google Scholar
  63. 63.
    Wojnowski, M., G. Sommer1, K. Pressel, and G. Beer, “3D eWLB—Horizontal and Vertical Interconnects for Integration of Passive Components”, IEEE/ECTC Proceedings, May 2013, pp. 2121–2125.Google Scholar
  64. 64.
    Liu, K., R. Frye, M. Hlaing, Y. Lee, H. Kim, G. Kim, S. Park, and B. Ahn, “High-Speed Packages with Imperfect Power and Ground Planes”, IEEE/ECTC Proceedings, May 2013, pp. 2046–2051.Google Scholar
  65. 65.
    Pachler, W., K. Pressel, J. Grosinger, G. Beer, W. Bösch, G. Holweg, C. Zilch, M. Meindl, “A Novel 3D Packaging Concept for RF Powered Sensor Grains”, IEEE/ECTC Proceedings, May 2014, pp. 1183–1188.Google Scholar
  66. 66.
    Osenbach, J., S. Emerich, L. Golick, S. Cate, M. Chan, S.W. Yoon, Y. Lin, and K. Wong, “Development of Exposed Die Large Body to Die Size Ratio Wafer Level Package Technology”, IEEE/ECTC Proceedings, May 2014, pp. 952–955.Google Scholar
  67. 67.
    Fan, X., “Wafer Level Packaging (WLP): Fan-in, Fan-out and Three-Dimensional Integration”, Proceedings of International Conference on Thermal, Mechanical and Multiphysics Simulation and Experiments in Micro-Electronics and Micro-Systems, April 2010, pp. 1–6.Google Scholar
  68. 68.
    Wojnowski, M., K. Pressel, and G. Beer, “Novel Embedded Z Line (EZL) Vertical Interconnect Technology for eWLB”, IEEE/ECTC Proceedings, May 2015, pp. 1071–1076.Google Scholar
  69. 69.
    Ishibashi, D., S. Sasaki, Y. Ishizuki, S. Iijima, Y. Nakata, Y. Kawano, T. Suzuki, and M. Tani, “Integrated Module Structure of Fan-out Wafer Level Package for Terahertz Antenna”, IEEE/ECTC Proceedings, May 2015, pp. 1084–1089.Google Scholar
  70. 70.
    Chen, S., S. Wang, J. Hunt, W. Chen, L. Liang, G. Kao, and A. Peng, “A Comparative study of a Fan Out Packaged Product: Chip First and Chip Last”, IEEE/ECTC Proceedings, May 2016, pp. 1483–1488.Google Scholar
  71. 71.
    Spinella, L., J. Im, and P. S. Ho, “Reliability Assessment of Fan-out Packages Using High Resolution Moiré Interferometry and Synchrotron X-ray Microdiffraction”, IEEE/ECTC Proceedings, May 2016, pp. 2016–2021.Google Scholar
  72. 72.
    Braun, T., K.-F. Becker, S. Raatz, M. Minkus, V. Bader, J. Bauer, R. Aschenbrenner, R. Kahle, L. Georgi, S. Voges, M. Wohrmann, and K.-D. Lang, “Foldable Fan-out Wafer Level Packaging”, IEEE/ECTC Proceedings, May 2016, pp. 19–24.Google Scholar
  73. 73.
    Takahashii, H., H. Nomai, N. Suzuki, Y. Nomura, A. Kasahara, N. Takano, and T. Nonaka, “Large Panel Level Fan Out Package Built Up Study with Film Type Encapsulation Material”, IEEE/ECTC Proceedings, May 2016, pp. 134–139.Google Scholar
  74. 74.
    Lau, J.H. 1997. The Roles of DNP (Distance to Neutral Point) on Solder Joint Reliability of Area Array Assemblies. Journal of Soldering & Surface Mount Technology 9 (2): 58–60.CrossRefGoogle Scholar
  75. 75.
    Lau, J.H., and R.S.W. Lee. 1999. Chip Scale Package. New York: McGraw-Hill Book Company.Google Scholar
  76. 76.
    Lau, J. H., M. Li, N. Fan, E. Kuah, Z. Li, K. Tan, T. Chen, et al., “Fan-out wafer-level packaging (FOWLP) of large chip with multiple redistribution-layers (RDLs)”, Proceedings of IMAPS Symposium, 2017, pp. 576–583.Google Scholar
  77. 77.
    Lau, J. H., M. Li, N. Fan, E. Kuah, Z. Li, K. Tan, T. Chen, et al., “Fan-out wafer-level packaging (FOWLP) of large chip with multiple redistribution-layers (RDLs)”, IMAPS Transactions Journal of Microelectronics and Electronic Packaging. Oct. 2017, pp. 123–131.Google Scholar
  78. 78.
    Lau, J. H., M. Li, Q. Li, I. Xu, T. Chen, Z. Li, K. Tan, X. Qing, C. Zhang, K. Wee. R. Beica, C. Ko, S. Lim, N. Fan, E. Kuah, K. Wu, Y. Cheung, E. Ng, X. Cao, J. Ran, H. Yang, Y. Chen, N. Lee, M. Tao, J. Lo, and R. Lee, “Design, Materials, Process, and Fabrication of Fan-Out Wafer-Level Packaging”, IEEE Transactions on CPMT. June, 2018, pp. 991–1002.Google Scholar
  79. 79.
    Lau, J. H., M. Li, D. Tian, N. Fan, E. Kuah, K. Wu, M. Li, et al., “Warpage and Thermal Characterization of Fan-out Wafer-Level ackaging”, IEEE/ECTC Proceedings, May 2017, pp. 595–602.Google Scholar
  80. 80.
    Lau, J. H., M. Li, D. Tian, N. Fan, E. Kuah, K. Wu, M. Li, J. Hao, Y. Cheung, Z. Li, K. Tan, R. Beica, T. Taylor, CT Lo, H. Yang, Y. Chen, S. Lim, NC Lee, J. Ran, X. Cao, S. Koh, and Q. Young, “Warpage and Thermal Characterization of Fan-Out Wafer-Level Packaging”, IEEE Transactions on CPMT, October 2017, pp. 1729–1738.Google Scholar
  81. 81.
    Li, M., Q. Li, J. H. Lau, N. Fan, E. Kuah, K. Wu, et al., “Characterizations of fan-out wafer-level packaging”, Proceedings of IMAPS Symposium, Oct. 2017, pp. 557–562.Google Scholar
  82. 82.
    Lim, S., Y. Liu, J. H. Lau, M. Li, “Challenges of ball-attach process using Flux for fan-out wafer/panel level (FOWL/PLP) packaging”, Proceedings of IWLPC, Oct. 2017, pp. S10_P3_1–7.Google Scholar
  83. 83.
    Kuah, E., W. Chan, J. Hao, N. Fan, M. Li, J. H. Lau, K. Wu, et al., “Dispensing challenges of large format packaging and some of its possible solutions”, IEEE/EPTC Proceedings, December 2017, pp. S27_1–6.Google Scholar
  84. 84.
    Hua, X., H. Xu, Z. Li, D. Chen, K. Tan, J. H. Lau, M. Li, et al., “Development of chip-first and die-up fan-out wafer-level packaging”, IEEE/EPTC Proceeding, December 2017, pp. S23_1–6.Google Scholar
  85. 85.
    Rogers, B., C. Scanlan, and T. Olson, “Implementation of a Fully Molded Fan-Out Packaging Technology”, Proceeding of IWLPC, October 2013, pp. S10_P1_1–6.Google Scholar
  86. 86.
    Bishop, C., B. Rogers, C. Scanlan, and T. Olson, “Adaptive Patterning Design Methodologies”, IEEE/ECTC Proceedings, May 2016, pp. 7–12.Google Scholar
  87. 87.
    Lau, J. H., M. Li, Y. Lei, M. Li, Q. Yong, Z. Cheng, T. Chen, I. Xu, et al., “Reliability of FOWLP with Large Chips and Multiple RDLs”, IEEE/ECTC Proceedings, May 2018, pp. 1568–1576.Google Scholar
  88. 88.
    Lau, J. H., “Recent Advances and Trends in Advanced Packaging”, Chip Scale Review, Vol. 21, May/June 2017, pp. 46–54.Google Scholar
  89. 89.
    Lau, J. H., “Recent Advances and New Trends in Flip Chip Technology”, ASME Transactions, Journal of Electronic Packaging, September 2016, Vol. 138, Issue 3, pp. 1–23.Google Scholar
  90. 90.
    Lau, J. H., Fan-Out Wafer-Level Packaging, Springer Book Company, 2018.Google Scholar
  91. 91.
    Hwang, T., D. Oh, E. Song, K. Kim, J. Kim, and S. Lee, “Study of Advanced Fan-Out Packages for Mobile Applications”, IEEE/ECTC Proceedings, May 2018, pp. 343–348.Google Scholar
  92. 92.
    Suk, K., S. Lee, J. Kim, S. Lee, H. Kim, S. Lee, P. Kim, D. Kim, D. Oh, and J. Byun, “Low Cost Si-less RDL Interposer Package for High Performance Computing Applications”, IEEE/ECTC Proceedings, May 2018, pp. 64–69.Google Scholar
  93. 93.
    You, S., S. Jeon, D. Oh, K. Kim, J. Kim, S. Cha, and G. Kim, “Advanced Fan-Out Package SI/PI/Thermal Performance Analysis of Novel RDL Packages”, IEEE/ECTC Proceedings, May 2018, pp. 1295–1301.Google Scholar
  94. 94.
    Huemoeller, R., and C. Zwenger. 2015. Silicon Wafer Integrated Fan-Out Technology, 34–37. Chip Scale Review: Mar/Apr.Google Scholar
  95. 95.
    Lin, Y., S. Wu, W. Shen, S. Huang, T. Kuo, A. Lin, T. Chang, H. Chang, S. Lee, C. Lee, J. Su, X. Liu, Q. Wu, and K. Chen, “An RDL-First Fan-out Wafer Level Package for Heterogeneous Integration Applications”, IEEE/ECTC Proceedings, May 2018, pp. 349–354.Google Scholar
  96. 96.
    Che, F. X., D. Ho, M. Ding, and D. MinWoo, “Study on Process Induced Wafer Level Warpage of Fan-Out Wafer Level Packaging”, IEEE/ECTC Proceedings, 2016, pp. 1879–1885.Google Scholar
  97. 97.
    Rao, V., C. Chong, D. Ho, D. Zhi, C. Choong, S. Lim, D. Ismael, and Y. Liang, “Development of High Density Fan Out Wafer Level Package (HD FOWLP) With Multi-layer Fine Pitch RDL for Mobile Applications”, IEEE/ECTC Proceedings, May 2016, pp. 1522–1529.Google Scholar
  98. 98.
    Li, H., A. Chen, S. Peng, G. Pan, and S. Chen, “Warpage Tuning Study for Multi-chip Last Fan Out Wafer Level Package”, IEEE/ECTC Proceedings, May 2017, pp. 1384–1391.Google Scholar
  99. 99.
    Chen, Z., F. Che, M. Ding, D. Ho, T. Chai, V. Rao, “Drop Impact Reliability Test and Failure Analysis for Large Size High Density FOWLP Package on Package”, IEEE/ECTC Proceedings, May 2017, pp. 1196–1203.Google Scholar
  100. 100.
    Ki, W., W. Lee, I. Lee, I. Mok, W. Do, M. Kolbehdari, A. Copia, S. Jayaraman, C. Zwenger, and K. Lee, “Chip Stackable, Ultra-thin, High-flexibility 3D FOWLP (3D SWIFT® Technology) for Hetero-integrated Advanced 3D WL-SiP”, IEEE/ECTC Proceedings, May 2018, pp. 580–586.Google Scholar
  101. 101.
    Cheng, W., C. Yang, J. Lin, W. Chen, T. Wang, and Y. Lee, “Evaluation of Chip-Last Fan-Out Panel Level Packaging with G2.5 LCD Facility Using FlexUPTM and Mechanical De-bonding Technologies”, IEEE/ECTC Proceedings, May 2018, pp. 386–391.Google Scholar
  102. 102.
    Shih, M., R. Chen, P. Chen, Y. Lee, K. Chen, I. Hu, T. Chen, L. Tsai, E. Chen, E. Tsai, D. Tarng, C. Hung, “Comparative Study on Mechanical and Thermal Performance of eWLB, M-Series™ and Fan-Out Chip Last Packages”, IEEE/ECTC Proceedings, May 2018, pp. 1670–1676.Google Scholar
  103. 103.
    Lee, C., J. Su, X. Liu, Q. Wu, J. Lin, P. Lin, C. Ko, Y. Chen, W. Shen, T. Kou, S. Huang, Y. Lin, K. Chen, and A. Lin, “Optimization of Laser Release Process for Throughput Enhancement of Fan-Out Wafer-Level Packaging”, IEEE/ECTC Proceedings, May 2018, pp. 1818–1823.Google Scholar
  104. 104.
    Zhang, H., X. Liu, S. Rickard, R. Puligadda, and T. Flaim, “Novel Temporary Adhesive Materials for RDL-First Fan-Out Wafer-Level Packaging”, IEEE/ECTC Proceedings, May 2018, pp. 1925–1930.Google Scholar
  105. 105.
    Lau, J. H., P. Tzeng, C. Lee, C. Zhan, M. Li, J. Cline, et al., “Redistribution layers (RDLs) for 2.5D/3D IC integration”, Proceedings of IMAPS Symposium, 2013, pp. 434–441.Google Scholar
  106. 106.
    Lau, J. H., P. Tzeng, C. Lee, C. Zhan, M. Li, J. Cline, et al., “Redistribution Layers (RDLs) for 2.5D/3D IC Integration”, IMAPS Transactions, Journal of Microelectronic Packaging, Vol. 11, No. 1, First Quarter 2014, pp. 16–24.Google Scholar
  107. 107.
    Garrou, P., and C. Huffman, “RDL: an integral part of today’s advanced packaging technologies”, Solid State Technology, May 2011, pp. 18–20.Google Scholar
  108. 108.
    Lau, J. H., “8 Ways to Make RDLs for FOW/PLP”, Chip Scale Review, vol. 22, May/Jun, 2018, pp. 11–19.Google Scholar
  109. 109.
    Ma, M., S. Chen, P. I. Wu, A. Huang, C. H. Lu, A. Chen, et al., “The development and the integration of the 5 µm to 1 µm half pitches wafer level Cu redistribution layers”, IEEE/ECTC Proceedings, 2016, pp. 1509–1614.Google Scholar
  110. 110.
    Kim, Y., J. Bae, M. Chang, A. Jo, J. Kim, S. Park, et al., “SLIMTM, high-density wafer-level fan-out package development with sub-micron RDL”, IEEE/ECTC Proceedings, 2017, pp. 18–13.Google Scholar
  111. 111.
    Hiner, D., M. Kolbehdari, M. Kelly, Y. Kim, W. Do, J. Bae, “SLIMTM advanced fan-out packaging for high-performance multi-die solutions”, IEEE/ECTC Proceedings, 2017, pp. 575–580.Google Scholar
  112. 112.
    Lin, Y., W. Lai, C. Kao, J. Lou, P. Yang, C. Wang, and C. Hseih, “Wafer warpage experiments and simulation for fan-out chip on substrate”, IEEE/ECTC Proceedings, May 2016, pp. 13–18.Google Scholar
  113. 113.
    Che, F., D. Ho, M. Z. Ding, and X. Zhang, “Modeling and design solutions to overcome warpage challenge for Fan-out wafer level packaging (FO-WLP) technology”, IEEE/EPTC Proceedings, Dec. 2015, pp. 2–4.Google Scholar
  114. 114.
    Che, F., D. Ho, M. Z. Ding, and D. R. MinWoo, “Study on process induced wafer level warpage of fan-out wafer level packaging”, IEEE/ECTC Proceedings, May 2016, pp. 1879–1885.Google Scholar
  115. 115.
    Hou, F., T. Lin, L. Cao, F. Liu, J. Li, X. Fan, and G. Zhang, “Experimental verification and optimization analysis of warpage for panel-level fan-out package”, IEEE Transactions on Components, Packaging, and Manufacturing Technology, vol. 7, no. 10, Oct. 2017, pp. 1721–1728.Google Scholar
  116. 116.
    Shen, Y., L. Zhang, W. Zhu, J. Zhou, and X. Fan, “Finite-element analysis and experimental test for a capped-die flip chip package design”, IEEE Transactions on Components, Packaging, and Manufacturing Technology, vol. 6, no. 9, Sept. 2016, pp. 1308–1316.Google Scholar
  117. 117.
    Lau, J. H., M. Li, Y. Lei, M. Li, I. Xu, T. Chen, S. Chen, et al., “Warpage Measurements and Characterizations of Fan-Out Wafer-Level Packaging with Large Chips and Multiple Redistributed Layers”, IEEE/ECTC Proceedings, May 2018, pp. 594–600.Google Scholar
  118. 118.
    Lau, J. H., M. Li, Y. Lei, M. Li, I. Xu, T. Chen, S. Chen, Q. Yong, J. Madhukumar, K. Wu, F. Fan, E. Kuah, Z. Li, K. Tan, W. Bao, A. Lim, R. Beica, C. Ko, and X. Cao, “Warpage Measurements and Characterizations of Fan-Out Wafer-Level Packaging with Large Chips and Multiple Redistributed Layers”, IEEE Transactions on Components, Packaging, and Manufacturing Technology, vol. 8, no. 10, Oct. 2018, pp. 1729–1737.Google Scholar
  119. 119.
    JEDEC Standard JESD22-B112A, Package Warpage Measurement of Surface-Mount Integrated Circuits at Elevated Temperature, October 2009.Google Scholar
  120. 120.
    Lau, J. H., Extracted from the 2017 IEEE/ECTC panel session: “Panel Fan-out Manufacturing: Why, When, and How?”.Google Scholar
  121. 121.
    Lau, J. H., M. Li, Q. Li, I. Xu, T. Chen, Z. Li, et al., “Design, Materials, Process, and Fabrication of Fan-Out Wafer-Level Packaging”, IEEE Transaction on CPMT, June 2018, pp. 991–1002.Google Scholar
  122. 122.
    Ko, C. T., H. Yang, J. H. Lau, M. Li, M. Li, C. Lin, et al., “Design, materials, process, and fabrication of fan-out panel-level heterogeneous integration”, IMAPS Transaction on Journal of Microelectronics and Electronic Packaging, Oct. 2018, pp. 141–147.Google Scholar
  123. 123.
    Lau, J. H., M. Li, Y. Lei, M. Li, I. Xu, T. Chen, et al., “Reliability of fan-out wafer-level heterogeneous integration”, IMAPS Transaction on Journal of Microelectronics and Electronic Packaging, Oct. 2018, pp. 148–162.Google Scholar
  124. 124.
    Souriau, J., O. Lignier, M. Charrier, and G. Poupon, “Wafer Level Processing Of 3D System in Package for RF and Data Applications”, IEEE/ECTC Proceedings, 2005, pp. 356–361.Google Scholar
  125. 125.
    Henry, D., D. Belhachemi, J-C. Souriau, C. Brunet-Manquat, C. Puget, G. Ponthenier, J. Vallejo, C. Lecouvey, and N. Sillon, “Low Electrical Resistance Silicon Through Vias: Technology and Characterization”, IEEE/ECTC Proceedings, 2006, pp. 1360–1366.Google Scholar
  126. 126.
    Hou, S., W. Chen, C. Hu, C. Chiu, K. Ting, T. Lin, W. Wei, W. Chiou, V. Lin, V. Chang, C. Wang, C. Wu, and D. Yu, “Wafer-Level Integration of an Advanced Logic-Memory System Through the Second-Generation CoWoS Technology”, IEEE Transactions on Electron Devices, October 2017, pp. 4071–4077.Google Scholar
  127. 127.
    Selvanayagam, C., J. H. Lau, X. Zhang, S. Seah, K. Vaidyanathan, and T. Chai, “Nonlinear Thermal Stress/Strain Analysis of Copper Fill TSV (Through Silicon Via) and Their Flip-Chip Microbumps”, IEEE/ECTC Proceedings, May 27–30, 2008, pp. 1073–1081.Google Scholar
  128. 128.
    Selvanayagam, C., J. H. Lau, X. Zhang, S. Seah, K. Vaidyanathan, and T. Chai, “Nonlinear Thermal Stress/Strain Analyses of Copper Filled TSV (Through Silicon Via) and Their Flip-Chip Microbumps”, IEEE Transactions on Advanced Packaging, Vol. 32, No. 4, November 2009, pp. 720–728.Google Scholar
  129. 129.
    Lau, J. H., and G. Tang, “Thermal Management of 3D IC Integration with TSV (Through Silicon Via)”, IEEE/ECTC Proceedings, May 2009, pp. 635–640.Google Scholar
  130. 130.
    Lau, J. H., Y. S. Chan, and R. S. W. Lee, “3D IC Integration with TSV Interposers for High-Performance Applications”, Chip Scale Review, Vol. 14, No. 5, September/October, 2010, pp. 26–29.Google Scholar
  131. 131.
    Lau, J. H., “TSV Manufacturing Yield and Hidden Costs for 3D IC Integration”, IEEE/ECTC Proceedings, May 2010, pp. 1031–1041.Google Scholar
  132. 132.
    Zhang, X., T. Chai, J. H. Lau, C. Selvanayagam, K. Biswas, S. Liu, D. Pinjala, et al., “Development of Through Silicon Via (TSV) Interposer Technology for Large Die (21 × 21 mm) Fine-pitch Cu/low-k FCBGA Package”, IEEE Proceedings of ECTC, May, 2009, pp. 305–312.Google Scholar
  133. 133.
    Chai, T.C., X. Zhang, J.H. Lau, C.S. Selvanayagam, D. Pinjala, et al. 2011. Development of Large Die Fine-Pitch Cu/low-k FCBGA Package with through Silicon via (TSV) Interposer. IEEE Transactions on CPMT 1 (5): 660–672.Google Scholar
  134. 134.
    Lau, J. H., et al, “Apparatus Having Thermal-Enhanced and Cost-Effective 3D IC Integration Structure with Through Silicon Via Interposer”. US Patent No: 8,604,603, Date of Patent: December 10, 2013.Google Scholar
  135. 135.
    Chien, H.C., J.H. Lau, Y. Chao, R. Tain, M. Dai, S.T. Wu, W. Lo, and M.J. Kao. 2012. Thermal Performance of 3D IC Integration with Through-Silicon Via (TSV). IMAPS Transactions, Journal of Microelectronic Packaging 9: 97–103.CrossRefGoogle Scholar
  136. 136.
    Chaware, R., K. Nagarajan, and S. Ramalingam, “Assembly and reliability challenges in 3D integration of 28 nm FPGA die on a large high-density 65 nm passive interposer”, IEEE/ECTC Proceedings, May 2012, pp. 279–283.Google Scholar
  137. 137.
    Banijamali, B., S. Ramalingam, K. Nagarajan, and R. Chaware, “Advanced reliability study of TSV interposers and interconnects for the 28 nm technology FPGA”, IEEE/ECTC Proceedings, May 2011, pp. 285–290.Google Scholar
  138. 138.
    Banijamali, B., S. Ramalingam, H. Liu, and M. Kim, “Outstanding and innovative reliability study of 3D TSV interposer and fine-pitch solder micro-bumps”, IEEE/ECTC Proceedings, May 2012, pp. 309–314.Google Scholar
  139. 139.
    Xie, J., H. Shi, Y. Li, Z. Li, A. Rahman, K. Chandrasekar, et al., “Enabling the 2.5D integration”, Proceedings of IMAPS International Symposium on Microelectronics, October 2012, pp. 254–267.Google Scholar
  140. 140.
    Banijamali, B., C. Chiu, C. Hsieh, T. Lin, C. Hu, S. Hou, et al., “Reliability Evaluation of a CoWoS-Enabled 3D IC Package”, IEEE/ECTC Proceedings, May 2013, pp. 35–40.Google Scholar
  141. 141.
    Chuang, Y., C. Yuan, J. Chen, C. Chen, C. Yang, W. Changchien, C. Liu, and F. Lee, “Unified Methodology for Heterogeneous Integration with CoWoS Technology”, IEEE/ECTC Proceedings, May 2013, pp. 852–859.Google Scholar
  142. 142.
    Lau, J. H., C. Lee, C. Zhan, S. Wu, Y. Chao, M. Dai, R. Tain, H. Chien, et al., “Low-Cost Through-Silicon Hole Interposers for 3D IC Integration”, IEEE Transactions on CPMT, Vol. 4, No. 9, September 2014, pp. 1407–1419.Google Scholar
  143. 143.
    Pendse, R. D., Semiconductor Device and Method of Forming Extended Semiconductor Device with Fan-Out Interconnect Structure to Reduce Complexity of Substrate, Filed in the US Patent Office on December 23, 2011, US 2013/0161833.Google Scholar
  144. 144.
    Yu, D., “Advanced system integration technology trends”, SiP Global Summit, SEMICON Taiwan, September 6, 2018.Google Scholar
  145. 145.
    Hong, J., K. Choi, D. Oh, S Park, S. Shao, H. Wang, Y. Niu, and V. Pham, “Design Guideline of 2.5D Package with Emphasis on Warpage Control and Thermal Management”, IEEE/ECTC Proceedings, May 2018, pp. 682–692.Google Scholar
  146. 146.
    Jeng, S.-P., S.-M. Chen, F.-C. Hsu, P.-Y. Lin, J.-H. Wang, T.-J. Fang, P. Kavle, and Y.-J. Lin, “High Density 3D Fanout Package for Heterogeneous Integration”, IEEE/VLSI Circuits Proceedings, August 2017, pp. T114–T115.Google Scholar
  147. 147.
    Hsu, F., J. Lin, S. Chen, P. Lin, J. Fang, J. Wang, and S. Jeng, “3D Heterogeneous Integration with Multiple Stacking Fan-Out Package”, IEEE/ECTC Proceedings, May 2018, pp. 337–342.Google Scholar
  148. 148.
    Chiu, C., Z. Qian, and M. Manusharow, “Bridge interconnect with air gap in package assembly”, US Patent No. 8,872,349, Filed on September 11, 2012, Patented on October 28, 2014.Google Scholar
  149. 149.
    Mahajan, R., R. Sankman, N. Patel, D. Kim, K. Aygun, Z. Qian, et al., “Embedded Multi-Die Interconnect Bridge (EMIB)—A High-Density, High-Bandwidth Packaging Interconnect”, IEEE/ECTC Proceedings, May 2016, pp. 557–565.Google Scholar
  150. 150.
    Podpod, A., J. Slabbekoorn, A. Phommahaxay, F. Duval, A. Salahouedlhadj, M. Gonzalez, K. Rebibis, R.A. Miller, G. Beyer, and E. Beyne, “A Novel Fan-Out Concept for Ultra-High Chip-to-Chip Interconnect Density with 20-μm Pitch”, IEEE/ECTC Proceedings, May 2018, pp. 370–378.Google Scholar
  151. 151.
    Wang, C. -T., T. -C. Tang, C. -W. Lin, C. -W. Hsu, J. -S. Hsieh, C. -H. Tsai, K. -C. Wu, H. -P. Pu, and D. Yu, “InFO_AiP Technology for High Performance and Compact 5G Millimeter Wave System Integration”, IEEE/ECTC Proceedings, May 2018, pp. 202–207.Google Scholar

Copyright information

© Springer Nature Singapore Pte Ltd. 2019

Authors and Affiliations

  1. 1.ASM Pacific TechnologyHong KongHong Kong

Personalised recommendations