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Heterogeneous Integrations on Silicon Substrates (TSV-Interposers)

  • John H. LauEmail author
Chapter

Abstract

Because of the drive of AI (artificial intelligence), ML (machine learning), and 5G, the semiconductors such as the CPU (central processor unit) or GPU (graphic processor unit), HBM (high bandwidth memory), and sliced field-programmable gate array (FPGA)’s density and I/Os increase and pad-pitch decreases. Even a 12 build-up layers (6-2-6) organic package substrate mentioned in Chap.  2 is not enough to support the sliced chips and a TSV (through-silicon via) interposer is needed [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28]. TSMC called this kind of structure CoWoS (chip-on-wafer-on substrate) [6, 7, 8, 9, 10, 11]. Leti [12, 13] called it SoW (system-on-wafer).

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Copyright information

© Springer Nature Singapore Pte Ltd. 2019

Authors and Affiliations

  1. 1.ASM Pacific TechnologyHong KongHong Kong

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