RANK-Swapping Unblocked Row (RSR) Memory Controller

  • Arun S. TigadiEmail author
  • Hansraj Guhilot
  • Pramod Naik
Conference paper
Part of the Lecture Notes on Data Engineering and Communications Technologies book series (LNDECT, volume 28)


The main parts of the current-day memory system are a memory controller and a memory device. The task of the controller is to coordinate the requests from the CPU, DMA, and other devices. Command bus and data bus act as a bridge between two components. The front end of the memory controller does the work of generating commands related to the respective request. The timing issue and arbitration of these commands are taken care by the back end of the memory controller. The critical requirement of these memory controllers is to provide service to all the requestors without violating timing issues. The real-time multi-core systems (Bui et al in Temporal isolation on multiprocessing architectures. IEEE, 2011) [1] have many resources shared between the cores. This makes timing analysis harder in case of these systems. We use different methods to analyze these systems and make the assumption that “Access latency of single request” doesn’t depend on different cores. The problem in deriving upper bounds is mainly due to the complex nature of multi-core systems [1]. These systems use DDR RAM as their main memory. These memories are partitioned into RANKS and BANKS which can support parallelism. Moreover, internal caching used by DRAM makes locality of references significant. The present memory controllers distribute memory request based on the command sequences generated, but in real time, this nature will not take advantage of locality. We will introduce a new design for a multi-core system for DDR devices. This employs RANK-swapping and open-row policies. The main advantage of this scheme is a significant reduction in the worst-case latency. This is mainly due to the creative RANK-switching mechanism. The memory is portioned into RANKS, BANKS, and rows to store an array of data. From this, we can isolate hard and soft requestors by assigning the same RANK to a respective type of requestors. This architectural improvisation improves the performance. Read–write latency can be taken out of the picture to improve bus utilization. By this technique, the latency for hard requestors is made predictable because it only depends upon a number of other requestors in the same RANK. Arbitration in hard requestor is mainly focused on latency in the worst case (Wu in Worst case analysis of DRAM latency in hard real-time systems, 2013) [2]. Arbitration for soft requestors is focused on throughput optimization.





I would like to thank Dr. Hansraj Guhilot for his motivation and valuable suggestions. I would also thank the principal, HOD E and C, and all the teaching and non-teaching staff of KLE Dr. M.S.S. CET, Belagavi, for their support in completing this work.


  1. 1.
    Bui D et al (2011) Temporal isolation on multiprocessing architectures. In: 48th ACM/EDAC/IEEE design automation conference (DAC), 2011. IEEEGoogle Scholar
  2. 2.
    Wu Z (2013) Worst case analysis of DRAM latency in hard real-time systems. MASc thesis. University of WaterlooGoogle Scholar
  3. 3.
    Paolieri M, Quinones E, Cazorla F, Valero M (2009) An analyzable memory controller for hard real-time CMPs. IEEE Embed Syst Lett 1(4):86–90CrossRefGoogle Scholar
  4. 4.
    Akesson B, Goossens K, Ringhofer M (2007) Predator: a predictable SDRAM memory controller. In: 5th IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis (CODES+ ISSS), 2007. IEEEGoogle Scholar
  5. 5.
    Ecco L, Tobuschat S, Saidi S, Ernst R (2014) A mixed critical memory controller using bank privatization and fixed priority scheduling. In: Proceedings of the 20th IEEE international conference on real-time computing systems and applications (RTCSA), Aug 2014Google Scholar
  6. 6.
    Wang DT (2005) Modern DRAM memory systems: performance analysis and scheduling algorithm. Ph.D. dissertation, The University of Maryland at College ParkGoogle Scholar
  7. 7.
    Kim S, Soontae K, Lee Y (2012) DRAM power-aware rank scheduling. In: Proceedings of the 2012 ACM/IEEE international symposium on low power electronics and design. ACMGoogle Scholar
  8. 8.
    JEDEC (2012) DDR3 SDRAM Standard JESD79-3F, July 2012Google Scholar
  9. 9.
    Reineke J et al (2011) PRET DRAM controller: bank privatization for predictability and temporal isolation. In: Proceedings of the 9th IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis (CODES+ISSS), 2011, pp 99–108Google Scholar
  10. 10.
    Bourgade R et al (2008) Accurate analysis of memory latencies for WCET estimation. In: 16th international conference on real-time and network systems (RTNS 2008)Google Scholar

Copyright information

© Springer Nature Singapore Pte Ltd. 2019

Authors and Affiliations

  1. 1.KLE Dr. M.S.S. CETBelagaviIndia
  2. 2.CoreEL Technologies PVT LTDBengaluruIndia

Personalised recommendations