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An Inter-Layer-Distance Based Routing Algorithm for 3D Network-on-Chip

  • Tong Zou
  • Chengyi Zhang
  • Xuefeng Peng
  • Yuanxi Peng
Conference paper
Part of the Communications in Computer and Information Science book series (CCIS, volume 994)

Abstract

The three-dimensional Network-on-Chip (3D NoC) has been proposed to resolve the complex on-chip communication issues in multicore systems by using die stacking technology in recent years. It is more difficult to guarantee performance in 3D NoC system than 2D because of stacking dies and the unequal thermal conductance of different logic layers. To ensure the system performance and availability, we proposes an Inter-Layer-Distance based Routing (ILDR) algorithm, which distributes the traffic according to the inter-layer-distance from source node to destination node. We simultaneously consider the buffer status and node temperature of neighbors on path to determine the horizontal route of the next hop. The simulation results show that the proposed ILDR algorithm can apparently reduce network latency and improve network throughput in different experimental traffic patterns. Although the energy consumption is increased, the Energy delay product (EDP) is reduced, so ILDR is a power-efficient solution for 3D NoC.

Keywords

Inter-layer distance 3D NoC Routing algorithm 

References

  1. 1.
    Micheli, G.D., Benini, L.: Network on chip: a new paradigm for systems on chip design. In: Design, Automation and Test in Europe Conference and Exhibition, pp. 418–419. IEEE (2002)Google Scholar
  2. 2.
    Pavlidis, V.F., Friedman, E.G.: 3-D topologies for networks-on-chip. In: SOC Conference, pp. 285–288. IEEE (2006)Google Scholar
  3. 3.
    Chen, K.C., Chao, C.H., Lin, S.Y., Wu, A.Y.: Traffic- and Thermal-Aware Routing Algorithms for 3D Network-on-Chip (3D NoC) systems. In: Palesi, M., Daneshtalab, M. (eds.) Routing Algorithms in Networks-on-Chip, pp. 307–338. Springer, New York (2014).  https://doi.org/10.1007/978-1-4614-8274-1_12CrossRefGoogle Scholar
  4. 4.
    Wu, J., Dong, D., Liao, X., Wang, L.: Chameleon: Adaptive energy-efficient heterogeneous network-on-chip. In: IEEE International Conference on Computer Design, pp. 419–422. IEEE (2015)Google Scholar
  5. 5.
    Wu, J., Dong, D., Wang, L.: HM-Mesh: energy efficient hybrid multiple network-on-chip. In: International Symposium on Computer, Consumer and Control, pp. 404–407. IEEE (2016)Google Scholar
  6. 6.
    Jheng, K.Y., Chao, C.H., Wang, H.Y., Wu, A.Y.: Traffic-thermal mutual coupling co-simulation platform for three-dimensional Network-on-Chip. In: International Symposium on VlSI Design Automation and Test, pp. 135–138. IEEE (2010)Google Scholar
  7. 7.
    Glass, C.J., Ni, L.M.: The turn model for adaptive routing. In: International Symposium on Computer Architecture, pp. 278–287. IEEE (1998)Google Scholar
  8. 8.
    Chiu, G.M.: The odd-even turn model for adaptive routing. IEEE Trans. Parallel Distrib. Syst. 11(7), 729–738 (2000)CrossRefGoogle Scholar
  9. 9.
    Ascia, G., Catania, V., Palesi, M., Patti, D.: Neighbors-on-path: a new selection strategy for on-chip networks. In: Embedded Systems for Real Time Multimedia, pp. 79–84. IEEE (2006)Google Scholar
  10. 10.
    Kuo, C.C., Chen, K.C., Chang, E.J., Wu, A.Y.: Proactive Thermal-Budget-Based Beltway Routing algorithm for thermal-aware 3D NoC systems. In: International Symposium on System on Chip, pp. 1–4. IEEE (2013)Google Scholar
  11. 11.
    Chao, C.H., Yin, T.C., Lin, S.Y., Wu, A.Y.: Transport layer assisted routing for non-stationary irregular mesh of thermal-aware 3D network-on-chip systems. In: SoC Conference, pp. 284–289. IEEE (2011)Google Scholar
  12. 12.
    Chen, K.C., Lin, S.Y., Hung, H.S., Wu, A.Y.: Topology-aware adaptive routing for non-stationary irregular mesh in throttled 3D NoC systems. IEEE Trans. Parallel Distrib. Syst. 24(10), 2109–2120 (2013)CrossRefGoogle Scholar
  13. 13.
  14. 14.
    Ascia, G., Catania, V., Palesi, M., et al.: Implementation and analysis of a new selection strategy for adaptive routing in networks-on-chip. IEEE Trans. Comput. 57(6), 809–820 (2008)MathSciNetCrossRefGoogle Scholar
  15. 15.
    Zeng, L., Pan, T., Jiang, X., Watanabe, T.: An efficient highly adaptive and deadlock-free routing algorithm for 3D network-on-chip. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. E99(A.7), 1334–1344 (2016)CrossRefGoogle Scholar

Copyright information

© Springer Nature Singapore Pte Ltd. 2019

Authors and Affiliations

  • Tong Zou
    • 1
  • Chengyi Zhang
    • 1
  • Xuefeng Peng
    • 2
  • Yuanxi Peng
    • 1
  1. 1.School of ComputerNational University of Defense TechnologyChangshaChina
  2. 2.School of Electronic InformationHunan Institute of Information TechnologyChangshaChina

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