Key Retrieval from AES Architecture Through Hardware Trojan Horse

  • Sivappriya ManivannanEmail author
  • N. Nalla AnandakumarEmail author
  • M. Nirmala DeviEmail author
Conference paper
Part of the Communications in Computer and Information Science book series (CCIS, volume 969)


The study of Hardware Trojan and its impact is a cutting edge research topic today. Hardware Trojan Horses (HTH) are inserted by an adversary either during design or fabrication phase of IC which does the malicious alterations in the circuit. The main objective of this paper is to insert two new hardware Trojan designs on cryptosystem and study its impact by calculating path delay, power consumption and area utilization. In particular, the proposed Trojan is designed using single trigger with multiple payloads structure. These designs are imposed to do the malicious action of fault injection on the penultimate mixcolumn of AES-128, which enables to extract the entire 128 bit secret key with minimum time of activation on the HTHs by performing Differential Fault Analysis (DFA). Both the Trojan inserted AES designs are implemented on the Xilinx Virtex-5 FPGAs. The proposed Trojan designs, HT1 and HT2 have minimal area overhead of 0.7% and 1.5% respectively with frequency overhead of 2% each. Provided, the models designed have a negligible effect on path delay and power consumption when compared to the original AES.


Hardware Trojan Horse (HTH) Differential Fault Analysis (DFA) AES Trojan detection FPGA 


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© Springer Nature Singapore Pte Ltd. 2019

Authors and Affiliations

  1. 1.Department of Electronics and Communication EngineeringAmrita School of Engineering, Coimbatore, Amrita Vishwa VidyapeethamCoimbatoreIndia
  2. 2.Hardware Security Research GroupSociety for Electronic Transactions and SecurityChennaiIndia

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