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Reducing Power in Register Files for CAM- and SRAM-Based Processor Units

  • K. MuralidharanEmail author
  • K. Sridevi
Conference paper
Part of the Lecture Notes in Networks and Systems book series (LNNS, volume 65)

Abstract

Power consumption reduction in out-of-order superscalar processor has become very important in recent era due to the utilization of superscalar processor in all portable systems. Register Files is the one of the power-hungry source in the out-of-order processor design. The proposed design of Register File using power gating technique reduces both static power and dynamic power dissipation. The new design of Register also includes with a minimal amount of redesign and verification efforts, the minimum level of design risk and least amount of hardware overhead and without any significant impact on the performance of the out-of-order superscalar processor.

Keywords

Out-of-order super scalar processor Register Files Power gating Low power 

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Copyright information

© Springer Nature Singapore Pte Ltd. 2019

Authors and Affiliations

  1. 1.Department of ECECoimbatore Institute of TechnologyCoimbatoreIndia
  2. 2.Department of ECECIT Sandwich Polytechnic CollegeCoimbatoreIndia

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