Reducing Power in Register Files for CAM- and SRAM-Based Processor Units
Power consumption reduction in out-of-order superscalar processor has become very important in recent era due to the utilization of superscalar processor in all portable systems. Register Files is the one of the power-hungry source in the out-of-order processor design. The proposed design of Register File using power gating technique reduces both static power and dynamic power dissipation. The new design of Register also includes with a minimal amount of redesign and verification efforts, the minimum level of design risk and least amount of hardware overhead and without any significant impact on the performance of the out-of-order superscalar processor.
KeywordsOut-of-order super scalar processor Register Files Power gating Low power
- 2.Kucuk G, Ponomarev D, Ghose K (2002) Low-complexity reorder buffer architecture. In: 16th ACM international conference on supercomputing (ICS’02), New York, June 2002, pp 57–66Google Scholar
- 3.Hu JS, Vijaykrishnan N, Irwin MJ (2004) Exploring wakeup-free instruction scheduling. In: Proceedings of the 10th international conference on high-performance computer architecture (HPCA-10 2004), 14–18 February 2004, Madrid, SpainGoogle Scholar
- 4.Hu Z, Buyuktosunoglu A, Srinivasan V, Zyuban V, Jacobson H, Bose P (2004) Microarchitectural techniques for power gating of execution units. In: International symposium on low power electronics and design, 2004Google Scholar
- 5.Stark J, Brown MD, Patt YN (2000) On pipelining dynamic instruction scheduling logic. In: Proceedings of the international symposium on microarchitecture, December 2000Google Scholar