Advertisement

Increasing the Verification Analysis Using Tool Assessment as Per DO-254

  • Manju NandaEmail author
  • P. Rajshekhar Rao
Conference paper
Part of the Lecture Notes in Networks and Systems book series (LNNS, volume 65)

Abstract

Programming under simulation-based testing remains the essential methods for utilitarian approval for HDL (hardware description language) plans. Code coverage which ensures to utilize simulation assets and a measure of test design. In this way, more target techniques, which utilize some all around characterized practical code measurements to play out a quantitative examination of simulation fulfillment, are proposed and quickly getting a response. For this reason, numerous utilitarian code measurements are proposed to confirm the design written in HDL. Keeping in mind the end goal to screen the code variation during simulation, a committed apparatus is required other than the test system. Finally, this paper includes the proposed well-known methodologies to achieve an accuracy of a test system using Code coverage.

Keywords

HDL RTL Coverage analysis VHDL Verification tool 

References

  1. 1.
    Ip CN (2000) Simulation coverage enhancement using test stimulus transformation. In: Proceedings of IEEE/ACM international conference on computer-aided design, digest of technical papers. IEEE Press, Piscataway, N.J., 2000, pp 127–133Google Scholar
  2. 2.
    Ho P-H et al (2000) Smart simulation using collaborative formal and simulation engines. In: Proceedings of IEEE/ACM international conference computer-aided design, digest of technical papers. IEEE Press, Piscataway, N.J., 2000, pp 120–126Google Scholar
  3. 3.
    Fournier L, Koyfman A, Levinger M (1999) Developing an architecture validation suite: application to the power PC architecture. In: Proceedings of 36th design automation conference. ACM Press, New York, 1999, pp 189–194Google Scholar
  4. 4.
    Malka Y, Ziv A (1998) Design reliability-estimation through statistical analysis of bug discovery data. In: Proceedings of 35th design automation conference. ACM Press, New York, 1998, pp 644–649Google Scholar
  5. 5.
    Arditi L, Clave G (2000) A semi-formal methodology for the functional validation of an industrial DSP system. In: Proceedings of IEEE international symposium on circuits and systems. IEEE Press, Piscataway, N.J., 2000, pp 205–208Google Scholar
  6. 6.
    Taylor S et al (1998) Functional verification of a multiple issue, out-of-order, superscalar Alpha processor—the DEC Alpha 21264 Microprocessor. In: Proceedings 35th design automation conference. ACM Press, New York, 1998, pp 638–643Google Scholar
  7. 7.
    Kantrowitz M, Noack LM (1996) I’m done simulating; now what? Verification coverage analysis and correctness checking of the DEC chip 21164 Alpha Microprocessor. In: Proceedings of 33rd design automation conference. ACM Press, New York, 1996, pp 325–330Google Scholar
  8. 8.
    Zhu H, Hall PV, May JR (1997) Software unit test coverage and adequacy. ACM Comput Surv 29(4):366-427CrossRefGoogle Scholar
  9. 9.
    Grinwald R et al (1998) User defined coverage—a tool supported methodology for design verification. In: Proceedings of 35th design automation conference. ACM Press, New York, 1998, pp 158–163Google Scholar
  10. 10.
    Vemuri R, Kalyanaraman R (1995) Generation of design verification tests from behavioral VHDL programs using path enumeration and constraint programming. IEEE Trans Very Large Scale Integr (VLSI) Syst 3(2):201–214CrossRefGoogle Scholar

Copyright information

© Springer Nature Singapore Pte Ltd. 2019

Authors and Affiliations

  1. 1.Aerospace Electronics and System Division, CSIR-NALBangaloreIndia
  2. 2.Department of AvionicsIST, JNTUKKakinadaIndia

Personalised recommendations