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Thin-Film Oxide Transistor by Liquid Process (3): TFTs with ZrInZnO Channel

High-Performance Solution-Processed ZrInZnO TFT
  • Tatsuya Shimoda
Chapter
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Abstract

In this chapter, we report on thin-film transistors (TFTs) with high performance and high stability using a solution-processed ZrInZnO (ZIZO) film as an active layer. In Sect. 18.1, the effects of adding Zr to In–Zn–O, particularly the electrical characteristics of their thin films and TFTs, were systematically investigated. The Zr addition effectively controlled oxygen vacancies because of the low standard electrode potential of Zr, which was confirmed by modifications in the optical bandgap energy, carrier concentration, and oxygen-vacancy density of the ZIZO thin films. Consequently, the off current decreased and the threshold voltage increased with increasing Zr content. The optimal ZIZO TFT was obtained at the Zr/In/Zn mole ratio of 0.05:2:1, and its “on/off” ratio, channel mobility, and subthreshold swing voltage were ~109, 6.23 cm2 V−1 s−1, and 0.19 V/dec, respectively. Not only the performance but also the bias–stress stability was improved as a result of the reduced interface charge trapping nature of ZIZO TFTs.

In Sect. 18.2, a polysilazane-based SiO2 gate insulator, which is also a solution processable material, is investigated to get the maximum out of a ZrInZnO semiconductor in a TFT. A smooth interface without defects was confirmed in the ZrInZnO/SiO2 system. The gate leakage current was reduced to 1 × 10−8 A/cm2 at 1 MV/cm. The resulting TFTs exhibited a field-effect mobility of 19–29 cm2 V−1 s−1 with a low leakage current of less than 9 × 10−11 A.

The third example of all-solution-processed TFT, in which all the layers were fabricated using simple solution process, is introduced in Sect. 18.3. In particular, our original combination of amorphous lanthanum zirconium oxide (LaZrO) and zirconium–indium–zinc oxide (ZrInZnO) films was used as a gate insulator and channel layer, respectively. In addition to that, a ruthenium oxide film was used both for the gate and source/drain electrodes. The ultraviolet–ozone (UV/O3) treatment was also adopted to a channel layer to facilitate precursor decomposition and condensation processes. As a result, the obtained on/off ratio, subthreshold swing voltage, and channel mobility were ∼6 × 105, 250 mV/decade, and 5.80 cm2 V−1 s−1, respectively.

As an evolution of all-solution-processed TFT, we tried to fabricate an all-solution-processed active-matrix transistor array for a EPD (electrophoretic display). That is described in Sect. 18.4. In the case of an active-matrix TFT backplane, not only TFT layers but also the other additional layers are required, so fabrication is more complicated and difficult compared with a sole TFT. The developed TFTs exhibited a good operation, and the active-matrix-driven electrophoretic displays (AM-EPDs) with the resolution of 101.6 ppi were successfully fabricated using an all-solution process. Bistable black/white images were confirmed in these AM-EPDs for the first time.

Keywords

Solution-processed ZrInZnO (ZIZO) film Polysilazane-based SiO2 gate insulator All-solution-processed TFT all-solution-processed active-matrix transistor array Standard electrode potential (SEP) 
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Authors and Affiliations

  • Tatsuya Shimoda
    • 1
  1. 1.Japan Advanced Institute of Science and TechnologyNomiJapan

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