Design of High-Gain CG–CS 3.1–10.6 GHz UWB CMOS Low-Noise Amplifier
A high-gain low-power CMOS low-noise amplifier is simulated using TSMC 0.18-µm CMOS technology. The cascade topology is used to get the high-gain and low-noise figure value. The source degeneration technique is used for the wideband matching. The circuit is simulated for 3.1–10.6 GHz in ultawideband. The simulated results show the maximum gain of 21.574 dB at 6.378 GHz and positive gain maintained during the entire frequency range. The highest noise figure value is 4.311 dB at 7.662 GHz, and the lowest value is 2.477 dB at 3.1 GHz. The matching circuit at input and output terminals shows the input return loss of 22.262 dB at 10.38 GHz, while the output return loss of 30.936 dB at 4.1 GHz. The circuit is simultaed at 1.2 V which draws the power consumption of 17.734 mW. The designed circuit shows the optimum value of gain, noise figure, matching and power consumption.
KeywordsLow-Noise amplifier Noise figure S parameters
- 2.Neeraja, A. R., & Yellampalli, S. S. (2017). Design of cascaded narrow band low noise amplifier. In 2017 International Conference on Electrical, Electronics, Communication, Computer, and Optimization Techniques (ICEECCOT), Mysuru (pp. 1–4).Google Scholar
- 3.Zulkifli, T. Z. A., Marzuki, A., & Murad, S. A. Z. (2017). UWB CMOS low noise amplifier for mode 1. In 2017 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia), Kuala Lumpur (pp. 117–120).Google Scholar
- 4.Saied, A. M., Abutaleb, M. M., Ibrahim, I. I., & Ragai, H. (2017). Ultra-low-power design methodology for UWB low-noise amplifiers. In 2017 29th International Conference on Microelectronics (ICM) (pp. 1–3).Google Scholar
- 7.Kumar, M., Kumar Deolia, V., & Kalra, D. (2016). DESIGN and simulation of UWB LNA using 0.18 μm CMOS technology. In 2016 2nd International Conference on Communication Control and Intelligent Systems (CCIS), Mathura (pp. 195–197).Google Scholar