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Performance Evaluation of Multi-operands Floating-Point Adder

  • Arvind Kumar
  • Sunil Kumar
  • Prateek Raj Gautam
  • Akshay Verma
  • Tarique Rashid
Conference paper
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 524)

Abstract

In this paper, an architecture is presented for a fused floating-point three operand adder unit. This adder executes two additions within a single unit. The purpose of this execution is to lessen total delay, die area, and power consumption in contrast with traditional addition method. Various optimization techniques including exponent comparison, alignment of significands, leading zero detection, addition, and rounding are used to diminish total delay, die area, and power consumption. In addition to this, the comparison is described of different blocks in term for die area, total delay, and power consumption. The proposed scheme is designed and implemented on Xilinx ISE Design 14.7 and synthesized on Synopsis.

Keywords

Floating-point adder Significand bits Exponent bits Total delay and Xilinx 

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Copyright information

© Springer Nature Singapore Pte Ltd. 2019

Authors and Affiliations

  • Arvind Kumar
    • 1
  • Sunil Kumar
    • 1
  • Prateek Raj Gautam
    • 1
  • Akshay Verma
    • 1
  • Tarique Rashid
    • 1
  1. 1.Motilal Nehru National Institute of Technology AllahabadAllahabadIndia

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