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A Comparative Analysis of Asymmetrical and Symmetrical Double Metal Double Gate SOI MOSFETs at the Zero-Temperature-Coefficient Bias Point

  • Amrish Kumar
  • Abhinav Gupta
  • Sanjeev Rai
Conference paper
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 524)

Abstract

The silicon-on-insulator (SOI) technology provides the higher current driving capability, low power consumptions, reduced SCEs and extensive scaling of the channel length. But SOI-based MOSFETs are weak in thermal stability like self-heating. In this paper, a comparative analysis of asymmetrical double metal double gate (ADMDG) and symmetrical double metal double gate (SDMDG) at the zero-temperature-coefficient (ZTC) bias point is proposed. ZTC is the bias point where the device constraints become free of variation in temperature. ADMDG and SDMDG devices are simulated by 2-D Atlas simulator. 2D-Atlas simulation revealed the figure of merit (FOMs) such as transconductance (gm), output conductance (gd), intrinsic gain (Av), on-current (Ion), off-current (Ioff), on–off current ratio (Ion/Ioff) and cutoff frequency (fT). The simulation results give the presence of inflection point of the devices. The variation of ZTC point for transconductance (ZTCgm) and drain current (ZTCIDS) for ADMDG and SDMDG MOSFETs is compared.

Keywords

ADMDG SDMDG Gate engineering SCEs Analog RF FOMs 

References

  1. 1.
    Scheinert, S., Paasch, G., & Schipanski, D. (1995). Analytical model and temperature dependence of the thin film SOI FET. Solid-state Electronics, 38(5), 949–959.CrossRefGoogle Scholar
  2. 2.
    Kumari, V. et al. (2012). Temperature dependent drain current model for Gate Stack Insulated Shallow Extension Silicon On Nothing (ISESON) MOSFET for wide operating temperature range. Microelectronics Reliability52.6, 974–983.CrossRefGoogle Scholar
  3. 3.
    Sahu, P. K., Mohapatra, S. K., & Pradhan, K. P. (2015). Zero temperature-coefficient bias point over wide range of temperatures for single-and double-gate UTB-SOI n-MOSFETs with trapped charges. Materials Science in Semiconductor Processing, 31, 175–183.CrossRefGoogle Scholar
  4. 4.
    Mohapatra, S. K., Pradhan, K. P., & Sahu, P. K. (2015). Temperature dependence inflection point in Ultra-Thin Si directly on Insulator (SDOI) MOSFETs: An influence to key performance metrics. Superlattices and Microstructures, 78, 134–143.CrossRefGoogle Scholar
  5. 5.
    Pradhan, K. P., & Sahu, P. K. (2016). Temperature dependency of double material gate oxide (DMGO) symmetric dual-k spacer (SDS) wavy FinFET. Superlattices and Microstructures, 89, 355–361.CrossRefGoogle Scholar
  6. 6.
    Pradhan, K. P., et al. (2015). Reliability analysis of charge plasma based double material gate oxide (DMGO) SiGe-on-insulator (SGOI) MOSFET. Superlattices and Microstructures, 85, 149–155.CrossRefGoogle Scholar
  7. 7.
    Roy, N. C., Gupta, A., & Rai, S. (2015). Analytical surface potential modeling and simulation of junction-less double gate (JLDG) MOSFET for ultra-low-power analog/RF circuits. Microelectronics Journal46.10, 916–922.CrossRefGoogle Scholar
  8. 8.
    ATLAS Device Simulator Software. (2015). Silvaco. CA, USA: Santa Clara.Google Scholar
  9. 9.
    International Technology Roadmap for Semiconductors. http://public.itrs.net.
  10. 10.
    Kumar, A. (2016). Analog and RF performance of a multigate FinFET at nano scale. Superlattices and Microstructures, 100, 1073–1080.CrossRefGoogle Scholar
  11. 11.
    Rai, S.. (2017). Reliability analysis of Junction-less Double Gate (JLDG) MOSFET for analog/RF circuits for high linearity applications. Microelectronics Journal, 64, 60–68.CrossRefGoogle Scholar
  12. 12.
    Kumar, A., Gupta, A., & Rai, S. (2017). Charge plasma based graded channel with dual material double gate JLT for enhance analog/RF performance. In 4th International Conference on Power, Control & Embedded Systems (ICPCES) (pp. 1–6–2017/11). IEEE.Google Scholar
  13. 13.
    Tan, T. H., & Goel, A. K. (2003). Zero-temperature-coefficient biasing point of a fully-depleted SOI MOSFET. Microwave and Optical Technology Letters, 37(5), 366–370.CrossRefGoogle Scholar

Copyright information

© Springer Nature Singapore Pte Ltd. 2019

Authors and Affiliations

  1. 1.Department of Electronics and Communication EngineeringMotilal Nehru National Institute of Technology AllahabadAllahabadIndia
  2. 2.Electronics Engineering DepartmentRajkiya Engineering CollegeSonbhadraIndia

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