Advertisement

3D NAND Flash Memories

Chapter
Part of the Springer Series in Advanced Microelectronics book series (MICROELECTR., volume 37)

Abstract

Nowadays, Solid State Drives consume an enormous amount of NAND Flash memories [1] causing a restless pressure on increasing the number of stored bits per mm2. Planar memory cells have been scaled for decades by improving process technology, circuit design, programming algorithms [2], and lithography.

References

  1. 1.
    F. Masuoka, M. Momodomi, Y. Iwata, R. Shirota, New ultra high density EPROM and flash EEPROM with NAND structure cell, in International Electron Devices Meeting, vol. 33 (1987), pp. 552–555Google Scholar
  2. 2.
    R. Micheloni, L. Crippa, A. Marelli, Inside NAND Flash Memories (Chap. 6) (Springer, 2010)CrossRefGoogle Scholar
  3. 3.
    T. Mizuno et al., Experimental study of threshold voltage fluctuation due to statistical variation of channel dopant number in MOSFET’s. IEEE Trans. Electron Devices 41(11), 2216–2221 (1994)ADSCrossRefGoogle Scholar
  4. 4.
    H. Kurata et al., The impact of random telegraph signals on the scaling of multilevel flash memories, in Symposium on VLSI Technology (2006)Google Scholar
  5. 5.
    C.M. Compagnoni et al., Ultimate accuracy for the NAND flash program algorithm due to the electron injection statistics. IEEE Trans. Electron Devices 55(10), 2695–2702 (2008)ADSCrossRefGoogle Scholar
  6. 6.
    S. Aritome, NAND Flash Memory Technologies. IEEE Press Series on Microelectronics System, Wiley-IEEE Press, Published on Dec 2015Google Scholar
  7. 7.
    S. Aritome, 3D flash memories, in International Memory Workshop 2011 (IMW 2011), short courseGoogle Scholar
  8. 8.
    R. Micheloni, L. Crippa, A. Marelli, Inside NAND Flash Memories (Chap. 5) (Springer, 2010)CrossRefGoogle Scholar
  9. 9.
  10. 10.
    R. Micheloni, L. Crippa, Multi-bit NAND flash memories for ultra high density storage devices (Chap 3), in Advances in Non-volatile Memory and Storage Technology, ed. by Y. Nishi (Woodhead Publishing, Sawston, 2014)CrossRefGoogle Scholar
  11. 11.
    R. Micheloni et al., High-capacity NAND flash memories: XLC storage and single-die 3D (Chap 7), in Memory Mass Storage, ed. by G. Campardo et al. (Springer, 2011)Google Scholar
  12. 12.
    H. Tanaka et al., Bit cost scalable technology with punch and plug process for ultra high density flash memory, in VLSI Symposium Technical Digest (2007), pp. 14–15Google Scholar
  13. 13.
    Y. Fukuzumi et al., Optimal integration and characteristics of vertical array devices for ultra-high density, bit-cost scalable flash memory, in IEDM Technical Digest (2007), pp. 449–452Google Scholar
  14. 14.
    M. Ishiduki et al., Optimal device structure for pipe-shaped BiCS flash memory for ultra high density storage device with excellent performance and reliability, in IEDM Technical Digest (2009), pp. 625–628Google Scholar
  15. 15.
    T. Maeda et al., Multi-stacked 1G cell/layer pipe-shaped BiCS flash memory, in Digest Symposium on VLSI Circuits, June 2009, pp. 22–23Google Scholar
  16. 16.
    R. Katsumata et al., Pipe-shaped BiCS flash memory with 16 stacked layers and multi-level-cell operation for ultra high density storage devices, in 2009 Symposium on VLSI Technology (2009), pp. 136–137Google Scholar
  17. 17.
    Y. Fukuzumi et al., Optimal integration and characteristics of vertical array devices for ultra-high density, bit-cost scalable flash memory, in IEDM Technical Digest (2007), pp. 449–452Google Scholar
  18. 18.
    H. Aochi, BiCS flash as a future 3-D non-volatile memory technology for ultra high density storage devices, in Proceedings of International Memory Workshop (2009), pp. 1–2Google Scholar
  19. 19.
    Y. Yanagihara et al., Control gate length, spacing and stacked layers number design for 3D-Stackable NAND flash memory 2, in IEEE IMW (2012), pp. 84–87Google Scholar
  20. 20.
    K. Takeuchi, Scaling challenges of NAND flash memory and hybrid memory system with storage class memory and NAND flash memory, in IEEE Custom Integrated Circuits Conference (CICC) (2013), pp. 1–6Google Scholar
  21. 21.
    A. Nitayama et al., Bit cost scalable (BiCS) flash technology for future ultra high density storage devices, in 2010 International Symposium on VLSI Technology Systems and Applications (VLSI TSA), Apr 2010, pp. 130–131Google Scholar
  22. 22.
    Y. Komori et al., Disturbless flash memory due to high boost efficiency on BiCS structure and optimal memory film stack for ultra high density storage device, in IEDM Technical Digest (2008), pp. 851–854Google Scholar
  23. 23.
    M. Ishiduki et al., Optimal device structure for pipe-shaped BiCS flash memory for ultra high density storage device with excellent performance and reliability, in IEDM Technical Digest (2009), pp. 625–628Google Scholar
  24. 24.
    T. Maeda et al., Multi-stacked 1G cell/layer pipe-shaped BiCS flash memory, in Digest Symposium on VLSI Circuits, June 2009, pp. 22–23Google Scholar
  25. 25.
    R. Katsumata et al., Pipe-shaped BiCS flash memory with 16 stacked layers and multi-level-cell operation for ultra high density storage devices, in 2009 Symposium on VLSI Technology (2009), pp. 136–137Google Scholar
  26. 26.
    J. Kim et al., Novel 3-D structure for ultra high density flash memory with VRAT (vertical-recess-array-transistor) and PIPE (planarized integration on the same plane), in 2008 IEEE Symposium on VLSI Technology (2008)Google Scholar
  27. 27.
    J. Kim et al., Novel vertical-stacked-array-transistor (VSAT) for ultra-high-density and cost-effective NAND flash memory devices and SSD (solid state drive), in 2009 IEEE Symposium on VLSI Technology (2009)Google Scholar
  28. 28.
    H.T. Lue, T.H. Hsu et al., A highly scalable 8-layer 3D Vertical-Gate (VG) TFT NAND flash using junction-free buried channel BE-SONOS device, in VLSI Symposia on Technology (2010)Google Scholar
  29. 29.
    J. Jang et al., Vertical cell array using TCAT (terabit cell array transistor) technology for ultra high density NAND flash memory, in 2009 IEEE Symposium on VLSI Technology (2009)Google Scholar
  30. 30.
    W. Cho et al., Highly reliable vertical NAND technology with biconcave shaped storage layer and leakage controllable offset structure, in 2010 Symposium on VLSI Technology (VLSIT) (2010), pp. 173–174Google Scholar
  31. 31.
    J. Elliott, E.S. Jung, Ushering in the 3D memory era with V-NAND, in Proceedings of Flash Memory Summit (Santa Clara, CA, 2013), www.flashmemorysummit.com
  32. 32.
    K.-T. Park, Three-dimensional 128 Gb MLC vertical NAND flash memory with 24-WL stacked layers and 50 MB/s high-speed programming, in IEEE ISSCC, Digest Technical Papers, Feb 2014, pp. 334–335Google Scholar
  33. 33.
    J.-W. Im, 128 Gb 3b/cell V-NAND flash memory with 1 Gb/s I/O rate, in IEEE International Solid-State Circuits Conference, Feb 2015, pp. 130–131Google Scholar
  34. 34.
    D. Kang et al., 256 Gb 3b/Cell V-NAND flash memory with 48 stacked WL layers, in IEEE International Solid-State Circuits Conference (ISSCC), Digest Technical Papers, Feb 2016, pp. 130–131Google Scholar
  35. 35.
    C. Kim et al., A 512 Gb 3b/cell 64-Stacked WL 3D V-NAND flash memory, in 2017 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), Feb 2017, pp. 202–203Google Scholar
  36. 36.
    K.-T. Park, Three-dimensional 128 Gb MLC vertical NAND flash memory with 24-WL stacked layers and 50 MB/s high-speed programming. IEEE J. Solid-State Circuit 50(1) (2015)ADSCrossRefGoogle Scholar
  37. 37.
    K.T. Park, A world’s first product of three-dimensional vertical NAND flash memory and beyond, in NVMTS, 27–29 Oct 2014Google Scholar
  38. 38.
    E. Choi et al., Device considerations for high density and highly reliable 3D NAND flash cell in near future, in IEEE International Electron Devices Meeting (2012), pp. 211–214Google Scholar
  39. 39.
    K. Shim et al., Inherent issues and challenges of program disturbance of 3D NAND flash cell, in IEEE International Memory Workshop (2012), pp. 95–98Google Scholar
  40. 40.
    J.-W. Im, 128 Gb 3b/cell V-NAND flash memory with 1 Gb/s I/O rate. J. Solid-State Circuit 51(1) (2016)Google Scholar
  41. 41.
    R. Yamashita et al., A 512 Gb 3b/cell flash memory on 64-Word-Line-Layer BiCS technology, in 2017 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), Feb 2017, pp. 196–197Google Scholar
  42. 42.
    T. Endoh et al., Novel ultra high density flash memory with a stacked-surrounding gate transistor (S-SGT) structured cell, in IEDM Technical Digest (2001), pp. 33–36Google Scholar
  43. 43.
    T. Endoh et al., Novel ultra high density flash memory with a stacked-surrounding gate transistor (S-SGT) structured cell. IEEE Trans. Electron Devices 50(4), 945–951 (2003)ADSCrossRefGoogle Scholar
  44. 44.
    T. Endoh et al., Floating channel type SGT flash memory, in The 1999 Joint International Meeting, Hawaii, vol. 99-2, Abstract No. 1323, 17–22 Oct 1999Google Scholar
  45. 45.
    M.S. Seo et al., The 3-dimensional vertical FG nand flash memory cell arrays with the novel electrical S/D technique using the extended sidewall control gate (ESCG), in Proceedings of IEEE International Memory Workshop (2010), pp. 1–4Google Scholar
  46. 46.
    M.S. Seo et al., 3-D vertical FG NAND flash memory with a novel electrical S/D technique using the extended sidewall control gate. IEEE Trans. Electron Devices 58(9) (2011)ADSCrossRefGoogle Scholar
  47. 47.
    S. Whang et al., Novel 3-dimensional dual control gate with surrounding floating-gate (DC-SF) NAND flash cell for 1 Tb file storage application, in Proceedings of International Electron Devices Meeting (IEDM) (2010), pp. 668–671Google Scholar
  48. 48.
    Y. Noh et al., A new metal control gate last process (MCGL process) for high performance DC-SF (dual control gate with surrounding floating gate), in 3D NAND flash memory in Symposium on VLSI Technology (2012), pp. 19–20Google Scholar
  49. 49.
    R. Micheloni, L. Crippa, Multi-bit NAND flash memories for ultra high density storage devices (Chap 3), in Advances in Non-volatile Memory and Storage Technology, ed. by Y. Nishi (Woodhead Publishing, 2014)CrossRefGoogle Scholar
  50. 50.
    R. Micheloni et al., High-capacity NAND flash memories: XLC storage and single-die 3D (Chap 7), in Memory Mass Storage, ed. by G. Campardo et al. (Springer, 2011)Google Scholar
  51. 51.
    H. Yoo et al., New read scheme of variable Vpass-read for dual control gate with surrounding floating gate (DC-SF) NAND flash cell, in Proceedings of 3rd IEEE International Memory Workshop (2011), pp. 1–4Google Scholar
  52. 52.
    S. Aritome et al., Advanced DC-SF cell technology for 3-D NAND flash. IEEE Trans. Electron Devices 60(4), 1327–1333 (2013)ADSCrossRefGoogle Scholar
  53. 53.
    M.S. Seo et al., A novel 3-D vertical FG nand flash memory cell arrays using the separated sidewall control gate (S-SCG) for highly reliable MLC operation, in Proceedings of 3rd IEEE International Memory Workshop (IMW) (2011), pp. 1–4Google Scholar
  54. 54.
    M.S. Seo et al., Novel concept of the three-dimensional vertical FG nand flash memory using the separated-sidewall control gate. IEEE Trans. Electron Devices 59(8), 2078–2084 (2012)ADSCrossRefGoogle Scholar
  55. 55.
    K. Parat, C. Dennison, A floating gate based 3D NAND technology with CMOS under array, in Conference on International Electron Devices Meeting (IEDM) (San Francisco, USA, Dec 2015)Google Scholar
  56. 56.
    T. Tanaka et al., A 768 Gb 3 b/cell 3D-floating-gate NAND flash memory, in 2016 IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers (San Francisco, USA, 2016), pp. 142–143Google Scholar
  57. 57.
    Eun-Seok Choi; Sung-Kye Park, Device considerations for high density and highly reliable 3D NAND flash cell in near future, in 2012 IEEE International Electron Devices Meeting (IEDM), 10–13 Dec 2012, pp. 9.4.1–9.4.4Google Scholar
  58. 58.
    Subirats et al., Impact of discrete trapping in high pressure deuterium annealed and doped poly-Si channel 3D NAND macaroni, in 2017 IEEE International Reliability Physics Symposium (IRPS)Google Scholar
  59. 59.
    L. Breuil, Improvement of poly-Si channel vertical charge trapping NAND devices characteristics by high pressure D2/H2 annealing, in 2016 IEEE 8th International Memory Workshop (IMW)Google Scholar
  60. 60.
    E. Capogreco et al., MOVPE In1-xGaxAs high mobility channel for 3-D NAND Memory, in 2015 IEEE International Electron Devices Meeting (IEDM)Google Scholar
  61. 61.
    J.G. Lisoni et al., Laser thermal anneal of polysilicon channel to boost 3D memory performance, in 2014 Symposium on VLSI Technology (VLSI-Technology), Digest of Technical PapersGoogle Scholar
  62. 62.
    Ki-Tae Park et al., Three-dimensional 128 Gb MLC vertical nand flash memory with 24-WL stacked layers and 50 MB/s high-speed programming. IEEE J Solid-State Circuits 50(1), 204–213 (2015)ADSCrossRefGoogle Scholar
  63. 63.
    J. Im et al., A 128 Gb 3b/cell V-NAND flash memory with 1 Gb/s I/O rate, in 2015 IEEE International Solid-State Circuits Conference, Digest of Technical Papers (ISSCC), Feb 2015, pp. 23–25Google Scholar
  64. 64.
    T. Tanaka et al., 7.7 A 768 Gb 3b/cell 3D-floating-gate NAND flash memory, in 2016 IEEE International Solid-State Circuits Conference (ISSCC) (San Francisco, CA, 2016), pp. 142–144Google Scholar
  65. 65.
    S. Aritome, NAND flash memory revolution, in 2016 IEEE 8th International Memory Workshop (IMW) (Paris, 2016), pp. 1–4Google Scholar
  66. 66.
    C.-P. Chen et al., Study of fast initial charge loss and its impact on the programmed states Vt distribution of charge-trapping NAND Flash, in 2010 IEEE International Electron Devices Meeting (IEDM), 6–8 Dec 2010, pp. 5.6.1, 5.6.4Google Scholar
  67. 67.
    H.-T. Lue, S.-Y. Wang, E.-K. Lai, K.-Y. Hsieh, R. Liu, C. Y. Lu, A BESONOS (Bandgap Engineered SONOS) NAND for post-floating gate era flash memory, in Symposium on VLSI Technology (2007)Google Scholar
  68. 68.
    K.-S. Shim et al., Inherent issues and challenges of program disturbance of 3D NAND flash cell, in 2012 4th IEEE International Memory Workshop (IMW), 20–23 May 2012, pp. 1–4Google Scholar
  69. 69.
    H.S. Yoo et al., Modeling and optimization of the chip level program disturbance of 3D NAND Flash memory, in 2013 5th IEEE International Memory Workshop (IMW), 26–29 May 2013, pp. 147–150Google Scholar
  70. 70.
    R. Micheloni (ed.), 3D Flash Memories (Springer, 2016)Google Scholar
  71. 71.
    K.-T. Park et al., 19.5 three-dimensional 128 Gb MLC vertical NAND Flash-memory with 24-WL stacked layers and 50 MB/s high-speed programming, in 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pp. 334–335,Feb 9-13, 2014Google Scholar
  72. 72.
    S. Aritome, Scaling challenges beyond 1Xnm DRAM and NAND Flash, in Joint Rump Session in VLSI Symposium 2012Google Scholar

Copyright information

© Springer Nature Singapore Pte Ltd. 2018

Authors and Affiliations

  1. 1.Storage Solutions, Microsemi CorporationVimercateItaly
  2. 2.IPCC, Industrial Property Cooperation CenterTokyoJapan

Personalised recommendations