ASIC and FPGA Synthesis

  • Vaibbhav TaraateEmail author


The chapter discusses the synthesis for the ASIC and FPGA. During the ASIC prototyping, FPGAs are used and how the ASIC designs can be migrated to FPGA which is discussed in this chapter. The chapter focuses on the important RTL design concepts design portioning, block-level and chip-level synthesis to start with. The design constraints used during the synthesis are discussed in this chapter with the practical scenarios. The chapter also focuses on the Synopsys DC commands used during synthesis. The gated clocks and implementation for the ASIC and FPGA are discussed with the implementation scenarios.


Synthesis ASIC FPGA Block-level synthesis Chip-level synthesis Constraints Area Speed Power Clock gating Partitioning Combinational loops Latch inference LUTs CLB Slice Standard cells Macros Hard macros Soft macros IPs FSM Optimization Logic duplication 


Copyright information

© Springer Nature Singapore Pte Ltd. 2019

Authors and Affiliations

  1. 1.1 Rupee S T (Semiconductor Training @ Rs. 1)PuneIndia

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