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RTL Design and Verification

  • Vaibbhav TaraateEmail author
Chapter

Abstract

The chapter discusses about RTL design and verification using Verilog. The RTL design and verification strategies are also discussed in this chapter. The chapter even discusses about the FSM performance improvement strategies. The chapter is useful to understand the role of the RTL design and verification engineer and important concepts.

Keywords

RTL Verilog Shift register Edge detector Priority checking Moore machine Mealy machine Performance improvement Verification Coverage Verification plan Test case Corner case 

Copyright information

© Springer Nature Singapore Pte Ltd. 2019

Authors and Affiliations

  1. 1.1 Rupee S T (Semiconductor Training @ Rs. 1)PuneIndia

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