RTL Design Guidelines

  • Vaibbhav TaraateEmail author


The design using Verilog constructs to achieve the better performance should be the objective of the RTL design engineer. The RTL team needs to use the RTL design guidelines while coding for efficient RTL. These guidelines can be tweaking of the RTL to improve the design performance or use of other techniques using Verilog constructs to improve the design performance. This chapter discusses the important guidelines and practical considerations during RTL design.


RTL Verilog If-else case always posedge negedge ASIC synthesis FPGA synthesis Multipliers Pipelining Multiple clock domain designs Gray counters Binary counters Resource utilization Resource sharing Gated clocks Register balancing Logic duplication 

Copyright information

© Springer Nature Singapore Pte Ltd. 2019

Authors and Affiliations

  1. 1.1 Rupee S T (Semiconductor Training @ Rs. 1)PuneIndia

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