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Testing at the Board Level

  • Vaibbhav TaraateEmail author
Chapter

Abstract

The chapter discusses the important points useful during the board bring-up stage to validate the SOC design. The chapter covers the debug planning, challenges, board testing for the single FPGA and multiple FPGAs. This chapter can give the understanding of use of the logic analyzer while testing the SOC design. The inter-FPGA connectivity issue, pin and location constraint issues are also discussed in this chapter.

Keywords

FPGA IO Configuration Multiple voltage domains IO pins Pin muxing LVDS Timing Gated clock Skew Glitches Impedance Signal integrity Latency Throughput Logic analyzer ChipScope Pro ILA API Oscilloscope 

Reference

Copyright information

© Springer Nature Singapore Pte Ltd. 2019

Authors and Affiliations

  1. 1.1 Rupee S T (Semiconductor Training @ Rs. 1)PuneIndia

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