Interconnect Delays and Timing

  • Vaibbhav Taraate


This chapter discusses the high-speed interconnects and their need in the design. If we consider about the complex SOC architecture, then the prototype using single FPGA is not always the feasible solution. The prototype needs to have the multiple FPGAs and the connectivity between them can be visualized using the bus topology. The high-speed interconnects between them can reduce the onboard delays and in turn improves the design performance. This chapter focuses on all these aspects, issue, challenges, and solutions to have the high-speed FPGA prototype using multiple FPGAs. The IO multiplexing, time budgeting, and interconnectivity between the FPGA are described using the practical considerations and design scenarios.


Interconnect Interface High speed Onboard delay Cable Switch matrix IO bandwidth Hyper-register HyperFlex Pin multiplexing IO multiplexing SERDES LVDS Deferred interconnect Star connection Ring connections 


Copyright information

© Springer Nature Singapore Pte Ltd. 2019

Authors and Affiliations

  1. 1.1 Rupee S T (Semiconductor Training @ Rs. 1)PuneIndia

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