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Design Integration and SOC Synthesis

  • Vaibbhav TaraateEmail author
Chapter

Abstract

This chapter discusses about the SOC synthesis and the design partitioning. To have the better prototype of the SOC as we know that we can have the multiple FPGA architectures. Under such circumstances, the better design partitioning can result into the high performance to have the proof of concept. The chapter key focus is to address the important aspects while partitioning the design. How to overcome the partitioning challenges and how to use the synthesis, place and route, and STA tools with incremental approach to validate the complex SOC designs are also discussed in this chapter!

Keywords

Partitioning Hardware and software partitioning Multiple FPGA designs Synthesis Incremental synthesis Manual partitioning Automatic partitioning P and R FPGA resources IO pads EDA tools Back-end tool 

References

Copyright information

© Springer Nature Singapore Pte Ltd. 2019

Authors and Affiliations

  1. 1.1 Rupee S T (Semiconductor Training @ Rs. 1)PuneIndia

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