SOC Prototyping Guidelines

  • Vaibbhav Taraate


The chapter discusses important design guidelines used during the SOC prototyping. The prototyping performance is based on how the design is partitioned into multiple FPGAs? What is IO speed and bandwidth? And how synchronizers are used? The chapter focuses on all these aspects in much more detail with the practical examples and considerations. Although most of the guidelines are discussed in the previous few chapters, in this chapter they are documented to have better understanding and their use during SOC prototyping.


Partitioning Register IO Combinational loop Oscillatory behavior Combinational output Unintentional latches Synchronous designs Asynchronous designs Multiple clock domain designs Clock gating Multiple FPGA partitioning TDM LVDS SERDES Combinational boundaries Sequential boundaries 


Copyright information

© Springer Nature Singapore Pte Ltd. 2019

Authors and Affiliations

  1. 1.1 Rupee S T (Semiconductor Training @ Rs. 1)PuneIndia

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