Static Timing Analysis

  • Vaibbhav TaraateEmail author


The chapter discusses the static timing analysis (STA) and the role of the STA engineer. The timing paths, maximum frequency calculations, input insertion delay, and output insertion delays are discussed in this chapter with the practical scenarios. The Synopsys PT commands are discussed in this chapter. How to achieve the timing performance to meet the timing constraints is also discussed with the practical scenarios. The chapter is useful for the ASIC and SOC designers to understand the STA concepts and techniques to overcome timing violations in the design. Even this chapter discusses the FPGA timing analysis.


STA DTA Timing paths Reg to output Input to output Reg to reg AT RT Slack Skew Setup Hold Clock to q delay Delay derating OCV Dynamic simulation Test vectors Coverage 


Copyright information

© Springer Nature Singapore Pte Ltd. 2019

Authors and Affiliations

  1. 1.1 Rupee S T (Semiconductor Training @ Rs. 1)PuneIndia

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