Static Timing Analysis
The chapter discusses the static timing analysis (STA) and the role of the STA engineer. The timing paths, maximum frequency calculations, input insertion delay, and output insertion delays are discussed in this chapter with the practical scenarios. The Synopsys PT commands are discussed in this chapter. How to achieve the timing performance to meet the timing constraints is also discussed with the practical scenarios. The chapter is useful for the ASIC and SOC designers to understand the STA concepts and techniques to overcome timing violations in the design. Even this chapter discusses the FPGA timing analysis.