Hybrid Mapping for Increased Security
Abstract
In this chapter, it is shown that the introduced hybrid application mapping can also be utilized to increase security in heterogeneous many-core systems. In the case of security, it is proposed to use the concept of spatial isolation enabled by invasion to close side channels. This requires a shift from the optimization criteria in the previous chapter. There, the hop distance between tasks is maximized to increase the run-time embeddability as one constraint graph typically allows for many concrete mappings. For spatial isolation, so-called shapes as a second intermediate representation besides the constraint graph are introduced. As these shapes represent tiles and adjacent routers, no communication constraints have to be evaluated during run-time mapping. This eases the run-time mapping and transforms it basically to a constrained 2D packing problem. Consequently, fast heuristics as well as SAT-based solvers which choose fitting shape incarnations from each application concurrently may be applied.
References
- 1.Aciiçmez O (2007) Yet another microarchitectural attack: exploiting I-cache. In: Proceedings of the ACM workshop on computer security architecture (CSAW), ACM, pp 11–18. https://doi.org/10.1145/1314466.1314469
- 2.Ahmadinia A, Bobda C, Koch D, Majer M, Teich J (2004) Task scheduling for heterogeneous reconfigurable computers. In: Proceedings of the symposium on integrated circuits and systems design (SBCCI), ACM, pp 22–27. https://doi.org/10.1145/1016568.1016582
- 3.Bazargan K, Kastner R, Sarrafzadeh M (2000) Fast template placement for reconfigurable computing systems. IEEE Des Test Comput 17(1):68–83. https://doi.org/10.1109/54.825678 CrossRefGoogle Scholar
- 4.Berre DL, Parrain A (2010) The Sat4j library, release 2.2. J Satisfiability, Boolean Model Comput (JSAT) 7(2–3):59–6, http://jsat.ewi.tudelft.nl/content/volume7/JSAT7_4_LeBerre.pdf
- 5.Biswas AK, Nandy SK, Narayan R (2015) Router attack toward NoC-enabled MPSoC and monitoring countermeasures against such threat. Circ Syst Sig Process 34(10):3241–3290. https://doi.org/10.1007/s00034-015-9980-0 CrossRefGoogle Scholar
- 6.Bolotin E, Cidon I, Ginosar R, Kolodny A (2004) QNoC: QoS architecture and design process for network on chip. J Syst Architect 50(2–3):105–128. https://doi.org/10.1016/j.sysarc.2003.07.004 CrossRefGoogle Scholar
- 7.Chou C, Ogras ÜY, Marculescu R (2008) Energy- and performance-aware incremental mapping for networks on chip with multiple voltage levels. IEEE Trans Comput Aided Des Integr Circuits Syst 27(10):1866–1879. https://doi.org/10.1109/TCAD.2008.2003301 CrossRefGoogle Scholar
- 8.Diguet J, Evain S, Vaslin R, Gogniat G, Juin E (2007) NOC-centric security of reconfigurable SoC. In: Proceedings of the international symposium on networks-on-chip (NOCS), IEEE, pp 223–232. https://doi.org/10.1109/NOCS.2007.32
- 9.Drescher G, Erhardt C, Freiling F, Götzfried J, Lohmann D, Maene P, Müller T, Verbauwhede I, Weichslgartner A, Wildermann S (2016) Providing security on demand using invasive computing. It Inf Technol 58(6):281–295. https://doi.org/10.1515/itit-2016-0032
- 10.Goens A, Khasanov R, Castrillon J, Hähnel M, Smejkal T, Härtig H (2017) Tetris: A multi-application run-time system for predictable execution of static mappings. In: Proceedings of the conference on languages, compilers and tools for embedded systems (SCOPES), ACM, pp 11–20. https://doi.org/10.1145/3078659.3078663
- 11.Graf S, Reimann F, Glaß M, Teich J (2014) Towards scalable symbolic routing for multi-objective networked embedded system design and optimization. In: Proceedings of the conference on hardware/software codesign and system synthesis (CODES+ISSS), ACM, pp 2:1–2:10. https://doi.org/10.1145/2656075.2656102
- 12.Heisswolf J, Weichslgartner A, Zaib A, Konig R, Wild T, Herkersdorf A, Teich J, Becker J (2013) Hardware supported adaptive data collection for networks on chip. In: International parallel and distributed processing symposium workshops PhD forum (IPDPSW), IEEE, pp 153–162. https://doi.org/10.1109/IPDPSW.2013.124
- 13.Heisswolf J, Zaib A, Weichslgartner A, König R, Wild T, Teich J, Herkersdorf A, Becker J (2013) Virtual networks – distributed communication resource management. Trans Reconfigurable Technol Syst (TRETS) 6(2):8:1–8:14. https://doi.org/10.1145/2492186
- 14.Jacob J (1992) Basic theorems about security. J Comput Secur 1(3–4):385–412. https://doi.org/10.3233/JCS-1992-13-409 MathSciNetCrossRefGoogle Scholar
- 15.Kemmerer RA (1983) Shared resource matrix methodology: An approach to identifying storage and timing channels. ACM Trans Comput Syst 1(3):256–277. https://doi.org/10.1145/357369.357374 CrossRefGoogle Scholar
- 16.Kocher PC (1996) Timing attacks on implementations of Diffie-Hellman, RSA, DSS, and other systems. In: Proceedings of the annual international cryptology conference (CRYPTO), Springer, Lecture Notes in Computer Science, vol 1109, pp 104–113. https://doi.org/10.1007/3-540-68697-5_9
- 17.Lampson BW (1973) A note on the confinement problem. Commun ACM 16(10):613–615. https://doi.org/10.1145/362375.362389 CrossRefGoogle Scholar
- 18.Lukasiewycz M, Glaß M, Reimann F, Teich J (2011) Opt4J: a modular framework for meta-heuristic optimization. In: Proceedings of the genetic and evolutionary computation conference (GECCO), ACM, pp 1723–1730. https://doi.org/10.1145/2001576.2001808
- 19.Masti RJ, Rai D, Marforio C, Capkun S (2014) Isolated execution on many-core architectures. IACR Cryptology ePrint Archive, p 136. http://eprint.iacr.org/2014/136
- 20.Masti RJ, Rai D, Ranganathan A, Müller C, Thiele L, Capkun S (2015) Thermal covert channels on multi-core platforms. In: Proceedings of the USENIX security symposium (USENIX), USENIX, pp 865–880. https://www.usenix.org/conference/usenixsecurity15/technical-sessions/presentation/masti
- 21.Pagani S, Bauer L, Chen Q, Glocker E, Hannig F, Herkersdorf A, Khdr H, Pathania A, Schlichtmann U, Schmitt-Landsiedel D, Sagi M, Sousa E, Wagner P, Wenzel V, Wild T, Henkel J (2016) Dark silicon management: An integrated and coordinated cross-layer approach. Inf Technol 58(6):297–307. https://doi.org/10.1515/itit-2016-0028
- 22.Palesi M, Holsmark R, Kumar S, Catania V (2006) A methodology for design of application specific deadlock-free routing algorithms for NoC systems. In: Proceedings of the conference on hardware/software codesign and system synthesis (CODES+ISSS), ACM, pp 142–147. https://doi.org/10.1145/1176254.1176289
- 23.Quan W, Pimentel AD (2015) A hybrid task mapping algorithm for heterogeneous MPSoCs. ACM Trans Embed Comput Syst (TECS) 14(1):14:1–14:25. https://doi.org/10.1145/2680542
- 24.Singh AK, Kumar A, Srikanthan T (2012) Accelerating throughput-aware runtime mapping for heterogeneous mpsocs. ACM Trans Des Autom Electron Syst (TODAES) 18(1):9. https://doi.org/10.1145/2390191.2390200 Google Scholar
- 25.Teich J, Fekete SP, Schepers J (1999) Compile-time optimization of dynamic hardware reconfigurations. In: Proceeding of the international conference on parallel and distributed processing techniques and applications (PDPTA), pp 1097–1103Google Scholar
- 26.Teich J, Fekete SP, Schepers J (2001) Optimization of dynamic hardware reconfigurations. J Supercomput 19(1):57–75. https://doi.org/10.1023/A:1011188411132
- 27.Wang Y, Suh GE (2012) Efficient timing channel protection for on-chip networks. In: Proceedings of the international symposium on networks-on-chip (NOCS), IEEE, pp 142–151. https://doi.org/10.1109/NOCS.2012.24
- 28.Weichslgartner A, Wildermann S, Götzfried J, Freiling F, Glaß M, Teich J (2016) Design-time/run-time mapping of security-critical applications in heterogeneous MPSoCs. In: Proceedings of the conference on languages, compilers and tools for embedded systems (SCOPES), ACM, pp 153–162. https://doi.org/10.1145/2906363.2906370
- 29.Zamfirescu C, Zamfirescu T (1992) Hamiltonian properties of grid graphs. SIAM J Discrete Math 5(4):564–570. https://doi.org/10.1137/0405046