Design of FPGA High-Speed Paralleling M Sequence

  • Zhi-Song Hao
  • Zhi-Ming Zheng
  • Rui-Liang Song
Conference paper
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 463)


To resolve the problem of processing clock frequency far below data generation rate for generating high-speed m sequence in FPGA, this paper adopts three methods of delay method, equivalent method and substitution method to design the parallel structure for generating paralleling m sequence and implements it on FPGA. The test results show that the generated paralleling m sequences fully meet the standard format requirements. This parallel structure achieves better application effects in the tests of scrambling and descrambling, BER, and coding and decoding in high-speed communication system.


PN sequence Parallel structure High-speed communication 


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Copyright information

© Springer Nature Singapore Pte Ltd. 2019

Authors and Affiliations

  1. 1.Beijing University of Aeronautics and AstronauticsBeijingChina
  2. 2.The 54th Research Institute of China Electronics Technology Group CorporationShijiazhuangChina

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