The Design and Optimization of DDR3 Controller Based on FPGA
Double Date Rate (DDR) SDRAM is the double rate synchronous dynamic random memory. It can sample twice on the rising and falling edges of the clock. Therefore, its sampling rate is theoretically twice the conventional SDRAM. However, due to other time cost, its bandwidth utilization is great lower than the theoretical value. DDR3 is the third generation and it has lower power consumption and higher sampling rate, so it is more suitable for data buffers than other SDRAM. Xilinx offers an IP core called MIG to simplify the interface of DDR3 SDRAM. This paper analyzes the problem of low bandwidth utilization, proposes an improved method, and designs a controller similar to the FIFO architecture based on the MIG core. In this way, the user-oriented interface is further simplified and the designer can use it easily. In addition, it has better portability.
KeywordsFPGA DDR3 controller MIG State machine
This work was supported by the Open Research Fund of State Key Laboratory of Space-Ground Integrated Information Technology under grant No. 2015_SGIIT_KFJJ_TX_02 and the National Science Foundations of China (No. 61671183, 91438205, 61771183).
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